Asynchronous consensus circuit with stacked linear or paraelectric planar capacitors

ABSTRACT

Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.

CLAIM FOR PRIORITY

This application is a continuation of, and claims the benefit ofpriority to U.S. patent application Ser. No. 17/647,963, filed on Jan.13, 2022, and titled, “Asynchronous Consensus Circuit usingMulti-Function Threshold Gate with Input Based Adaptive Threshold,” andwhich is incorporated by reference in its entirety.

BACKGROUND

Logic circuits can be categorized as synchronous logic or asynchronouslogic. Synchronous logic uses a global clock circuit to synchronizevarious logic components. For example, outputs of a combinational logicblock are sampled by latches or flip-flops by a clock to generatesynchronized data. Asynchronous logic does not use a global clock tosynchronize its various logic components. Instead, asynchronous logicuse handshaking protocols as data propagates from one logic component toanother. Existing asynchronous logic use stacks of transistors betweenpower supply rail and ground rail. Such circuits are challenging to usein low voltage conditions.

The background description provided here is for the purpose of generallypresenting the context of the disclosure. Unless otherwise indicatedhere, the material described in this section is not prior art to theclaims in this application and are not admitted to be prior art byinclusion in this section.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments of the disclosure will be understood more fully from thedetailed description given below and from the accompanying drawings ofvarious embodiments of the disclosure, which, however, should not betaken to limit the disclosure to the specific embodiments, but are forexplanation and understanding only.

FIG. 1 illustrates a set of plots and showing behavior of aferroelectric capacitor, a paraelectric capacitor, and a linearcapacitor.

FIG. 2A illustrates a 2-input consensus element (c-element) comprising a3-input minority gate and an inverter, where an adjustable thresholdgate is programmed as a 3-input minority gate, in accordance with someembodiments.

FIG. 2B illustrates a 3-input c-element comprising a 5-input minoritygate and an inverter, where an adjustable threshold gate is programmedas a 5-input minority gate, in accordance with some embodiments.

FIG. 3A illustrates a 2-input c-element comprising a 3-input majoritygate, where an adjustable threshold gate is programmed as a 3-inputmajority gate, in accordance with some embodiments.

FIG. 3B illustrates a 3-input c-element comprising a 5-input majoritygate, where an adjustable threshold gate is programmed as a 5-inputmajority gate, in accordance with some embodiments.

FIG. 4 illustrates an 8-input completion tree comprising c-elements, inaccordance with some embodiments.

FIG. 5 illustrates a 16-input completion tree comprising the 8-inputcompletion trees and a c-element, in accordance with some embodiments.

FIG. 6 illustrates an 8-input validity tree comprising OR-gates andc-elements, in accordance with some embodiments.

FIG. 7 illustrates a 16-input validity tree comprising the 8-inputvalidity tree and a c-element, in accordance with some embodiments.

FIG. 8A illustrates a 2-input adjustable threshold gate with linear orparaelectric capacitors and a pull-up device on a summing node, inaccordance with some embodiments.

FIG. 8B illustrates a 2-input adjustable threshold gate with linear orparaelectric capacitors and a pull-down device on a summing node, inaccordance with some embodiments.

FIG. 9A illustrates a 3-input adjustable threshold gate with linear orparaelectric capacitors and a pull-up device on a summing node, inaccordance with some embodiments.

FIG. 9B illustrates a 3-input adjustable threshold gate with linear orparaelectric capacitors and a pull-down device on a summing node, inaccordance with some embodiments.

FIG. 10A illustrates a 5-input adjustable threshold gate with linear orparaelectric capacitors and a pull-up device on a summing node, inaccordance with some embodiments.

FIG. 10B illustrates a 5-input adjustable threshold gate with linear orparaelectric capacitors and a pull-down device on a summing node, inaccordance with some embodiments.

FIG. 11 illustrates a 2-input adjustable threshold gate withferroelectric capacitors and a pull-down device and a pull-up device ona summing node, in accordance with some embodiments.

FIG. 12 illustrates a 3-input adjustable threshold gate withferroelectric capacitors and a pull-down device and a pull-up device ona summing node, in accordance with some embodiments.

FIG. 13 illustrates a 5-input adjustable threshold gate withferroelectric capacitors and a pull-down device and a pull-up device ona summing node, in accordance with some embodiments.

FIG. 14 illustrates a planar linear capacitor structure, in accordancewith some embodiments.

FIG. 15A illustrates a non-planar linear capacitor structure, inaccordance with some embodiments.

FIG. 15B illustrates a non-planar linear capacitor structure withoutconductive oxides, in accordance with some embodiments.

FIG. 16A illustrates a multi-input capacitive circuit with stackedplanar capacitor structure, wherein the multi-input capacitive circuitincludes a pull-up device, in accordance with some embodiments.

FIG. 16B illustrates a multi-input capacitive circuit with stackedplanar capacitor structure, wherein the multi-input capacitive circuitincludes a pull-down device, in accordance with some embodiments.

FIG. 17A illustrates a multi-input capacitive circuit with stackednon-planar capacitor structure, wherein the multi-input capacitivecircuit includes a pull-up device, in accordance with some embodiments.

FIG. 17B illustrates a multi-input capacitive circuit with stackednon-planar capacitor structure, wherein the multi-input capacitivecircuit includes a pull-up device, in accordance with some embodiments.

FIG. 18A illustrates a planar ferroelectric or paraelectric capacitorstructure, in accordance with some embodiments.

FIG. 18B illustrates three planar ferroelectric or paraelectriccapacitor structures, respectively, in accordance with some embodiments.

FIG. 19A illustrates a non-planar ferroelectric or paraelectriccapacitor structure, in accordance with some embodiments.

FIG. 19B illustrates a non-planar ferroelectric or paraelectriccapacitor structure without conductive oxides, in accordance with someembodiments.

FIG. 20 illustrates a multi-input capacitive circuit with stacked planarferroelectric or paraelectric capacitor structure, wherein themulti-input capacitive circuit includes a pull-up device and a pull-downdevice, in accordance with some embodiments.

FIG. 21 illustrates a multi-input capacitive circuit with stackednon-planar ferroelectric or paraelectric capacitor structure wherein themulti-input capacitive circuit includes a pull-up device and a pull-downdevice, in accordance with some embodiments.

FIG. 22 illustrates a high-level architecture of an artificialintelligence (AI) machine comprising a compute die stacked with a memorydie, wherein the compute die includes a c-element, completion tree,and/or validity tree with a multi-input capacitive circuit withconfigurable threshold, in accordance with some embodiments.

FIG. 23 illustrates an architecture of a computational block comprisinga compute die stacked with a memory die, wherein the compute dieincludes a c-element, completion tree, and/or validity tree with amulti-input capacitive circuit with configurable threshold, inaccordance with some embodiments.

FIG. 24 illustrates a system-on-chip (SOC) that uses a c-element,completion tree, and/or validity tree with a multi-input capacitivecircuit with configurable threshold, in accordance with someembodiments.

DETAILED DESCRIPTION

Some embodiments describe asynchronous circuits using threshold gate(s)and/or majority gate(s) (or minority gate(s)). The new class ofasynchronous circuits can operate at lower power supply levels (e.g.,less than 1V on advanced technology nodes) because stack of devicesbetween a supply node and ground are significantly reduced compared totraditional asynchronous circuits. The asynchronous circuits here resultin area reduction (e.g., 3× reduction compared to traditionalasynchronous circuits) and provide higher throughput/mm² (e.g., 2×higher throughput compared to traditional asynchronous circuits). Thethreshold gate(s), majority/minority gate(s) can be implemented usingcapacitive input circuits. The capacitors of the capacitive inputcircuits can have linear dielectric or nonlinear polar material (e.g.,paraelectric or ferroelectric) as dielectric. While the circuits hereare described with reference to asynchronous circuits, the circuits canalso be used in synchronous circuits. For example, combinational logicassociated with synchronous circuits can use the asynchronous circuitsdiscussed herein. In some embodiments, input signals to threshold ormajority gates can be clock signals, which allow these asynchronouscircuits to operate as synchronous circuits.

Some embodiments describe a consensus element (c-element) that outputs aconsensus of inputs. For example, when inputs are all logic 1, then theoutput of the c-element is logic 1 and when inputs are all logic 0, thenthe output of the c-element is logic 0. In some embodiments, the outputis state-holding when all inputs are not the same logic value. Forexample, a 3-input c-element is state holding when all three inputs arenot the same logical value. In this case the output will be the outputfrom a previous state. In some embodiments, the c-element is implementedwith a majority or minority gate. As discussed herein, the majority orminority gate may be implemented by adjusting a threshold of acapacitive input circuit.

Some embodiments describe a completion tree which is a network or treeof c-elements. The output of the completion tree is a logic 1 when allinputs to the completion tree are logic 1, in accordance with someembodiments. The output of the completion tree is a logic 0 when allinputs to the completion tree are a logic 0, in accordance with someembodiments. The output of the completion tree is state-holding when allinputs are not the same logic value.

Some embodiments describe a validity tree. In some embodiments, thevalidity tree comprises OR-gates and c-elements coupled in a tree-likearrangement where the OR gates receive the inputs and the output of theOR gates are input to the c-elements. In some embodiments, the OR gatesare implemented as threshold gates whose threshold is programmed oradjusted to generate an OR function. An output of a validity tree islogic 1 when all input bits are valid, in accordance with someembodiments. The output of the validity tree is logic 0 when all inputbits are neutral. When the inputs bits are either valid or neutral, theoutput of the validity tree holds its state, in accordance with someembodiments. In various embodiments, an individual input comprises twobits, ‘f’ and ‘t’. For example, a data input channel X includes a firstbit X.f and a second bit X.t. An individual input X has a valid 0 stateif X.f is logic 1 and if X.t is logic 0, in accordance with someembodiments. An individual input X has a valid 1 state if X.f is logic 0and if X.t is logic 1, in accordance with some embodiments. Anindividual input X has a neutral state if X.f is logic 0 and if X.t islogic 0, in accordance with some embodiments.

Some embodiments provide an apparatus and configuring scheme wherecapacitive input circuit can be programmed to perform different logicfunctions by adjusting the switching threshold of the capacitive inputcircuit. These capacitive circuits can become the basic building blocksfor the c-element, the completion tree, and/or the validity tree.Digital inputs are received by respective capacitors on first terminalsof those capacitors. In various embodiments, these capacitors compriselinear dielectric, paraelectric dielectric material, or ferroelectricdielectric material. The second terminals of the capacitors areconnected to a summing node, in accordance with various embodiments. Insome embodiments, a pull-up and/or pull-down device is coupled to thesumming node. The pull-up and/or pull-down devices are controlledseparately.

In some embodiments, during a reset phase, depending on the type ofcapacitor (linear, paraelectric, or ferroelectric), the inputs to thecapacitive input circuit are conditioned and the pull-up or pull-downdevice is turned on or off. As such the threshold of the capacitiveinput circuit is set. In some embodiments, when the capacitors havelinear dielectric or paraelectric dielectric, one of pull-up orpull-down devices may couple to the summing node. In some embodiments,when the capacitors have ferroelectric dielectric then both pull-up andpull-down devices may couple to the summing node. In one suchembodiment, the pull-up and pull-down devices are turned on and off in asequence and inputs are conditioned to adjust the threshold of thecapacitive input circuit. After the reset phase, an evaluation phasefollows, in accordance with some embodiments. In the evaluation phase,the output of the capacitive input circuit is determined based on theinputs and the logic function configured during the reset phase, inaccordance with various embodiments. For example, the capacitive inputcircuit may operate as a NAND/AND gate, NOR/OR gate, majority/minority,threshold gate, or other complex gates based on its thresholdconfiguration. In various embodiments, during the evaluation phase, thepull-up and pull-down devices coupled to the summing node are turnedoff. In some embodiments, all input capacitors have the same capacitance(e.g., same weight or ratio). In some embodiments, the input capacitorsmay have different capacitance. In that case, the switching thresholdfor the input capacitor circuit is modified differently by the resetphase. In some embodiments, a different logic gate can be realized bysequencing turning on/off of the pull-up and pull-down devices andchanging inputs to the input capacitor circuit during the reset phase.

While the embodiments are described with reference to up-to 5-inputcapacitive circuit using equal ratio for the capacitance, the same ideacan be expanded to any number of input capacitive circuit with equal orunequal ratio for capacitances. In various embodiments, the capacitancesare nonlinear capacitors. For example, instead of linear dielectric, thecapacitors include nonlinear dielectric material. Examples of nonlineardielectric material include ferroelectric material and paraelectricmaterial.

In some embodiments, the capacitor are planar capacitors. In someembodiments, the capacitors are pillar or trench capacitors. In someembodiments, the capacitors are vertically stacked capacitors to reducethe overall footprint of the multi-input capacitive circuit. In someembodiments, the transistors (MP1 and/or MN1) that charge or dischargethe summing node n1 are planar or non-planar transistors. In someembodiments, transistors MP1 and/or MN1 are fabricated in the front-endof the die on a substrate. In some embodiments, when the capacitors haveferroelectric material, one of the transistors (e.g., MP1 or MN1) isfabricated in the front-end of the die while another one of thetransistors is fabricated in the backend such that the stack ofcapacitors is between the frontend of the die and the backend of the dieor between the two transistors. As such, the footprint of themulti-input capacitive circuit may be a footprint of a single transistoror slightly more than that. The various possible implementations of thec-element, the completion tree, and the validity tree using theadjustable threshold gate-based logic circuit allows for lower power andsmaller area based asynchronous circuits compared to traditionalasynchronous circuits.

In the following description, numerous details are discussed to providea more thorough explanation of embodiments of the present disclosure. Itwill be apparent, however, to one skilled in the art, that embodimentsof the present disclosure may be practiced without these specificdetails. In other instances, well-known structures and devices are shownin block diagram form, rather than in detail, to avoid obscuringembodiments of the present disclosure.

Note that in the corresponding drawings of the embodiments, signals arerepresented with lines. Some lines may be thicker, to indicate moreconstituent signal paths, and/or have arrows at one or more ends, toindicate primary information flow direction. Such indications are notintended to be limiting. Rather, the lines are used in connection withone or more exemplary embodiments to facilitate easier understanding ofa circuit or a logical unit. Any represented signal, as dictated bydesign needs or preferences, may actually comprise one or more signalsthat may travel in either direction, and may be implemented with anysuitable type of signal scheme.

It is pointed out that those elements of the figures having the samereference numbers (or names) as the elements of any other figure canoperate or function in any manner like that described but are notlimited to such.

FIG. 1 illustrates a set of plots showing behavior of a ferroelectriccapacitor, a ferroelectric capacitor, and a linear capacitor. Plot 100compares the transfer function for a linear capacitor, a ferroelectric(PE) capacitor (a nonlinear capacitor) and a ferroelectric (FE)capacitor (a nonlinear capacitor). Here, x-axis is input voltage orvoltage across the capacitor, while the y-axis is the charge on thecapacitor. The ferroelectric material can be any suitable low voltage FEmaterial that allows the FE material to switch its state by a lowvoltage (e.g., 100 mV). Threshold in the FE material has a highlynonlinear transfer function in the polarization vs. voltage response.The threshold is related to: a) nonlinearity of switching transferfunction; and b) the squareness of the FE switching. The nonlinearity ofswitching transfer function is the width of the derivative of thepolarization vs. voltage plot. The squareness is defined by the ratio ofthe remnant polarization to the saturation polarization, perfectsquareness will show a value of 1. The squareness of the FE switchingcan be suitably manipulated with chemical substitution. For example, inPbTiO3 a P-E (polarization-electric field) square loop can be modifiedby La or Nb substitution to create an S-shaped loop. The shape can besystematically tuned to ultimately yield a nonlinear dielectric. Thesquareness of the FE switching can also be changed by the granularity ofan FE layer. A perfectly epitaxial, single crystalline FE layer willshow higher squareness (e.g., ratio is closer to 1) compared to apolycrystalline FE. This perfect epitaxial can be accomplished usinglattice matched bottom and top electrodes. In one example, BiFeO (BFO)can be epitaxially synthesized using a lattice matched SrRuO3 bottomelectrode yielding P-E loops that are square. Progressive doping with Lawill reduce the squareness.

Plot 120 shows the charge and voltage relationship for a ferroelectriccapacitor. A capacitor with ferroelectric material (also referred to asa FEC) is a nonlinear capacitor with its potential V_(F)(Q_(F)) as acubic function of its charge. Plot 120 illustrates characteristics of anFEC. Plot 120 is a charge-voltage (Q-V) plot for a block ofPb(Zr_(0.5)Ti_(0.5))O₃ of area (100 nm)² and thickness 30 nm(nanometer). Plot 120 shows local extrema at +/−V_(o) indicated by thedashed lines. Here, the term V_(c) is the coercive voltage. In applyinga potential V across the FEC, its charge can be unambiguously determinedonly for |V|>V_(o). Otherwise, the charge of the FEC is subject tohysteresis effects.

In some embodiments, the FE material comprises a perovskite of the typeABO₃, where ‘A’ and ‘B’ are two cations of different sizes, and ‘O’ isoxygen which is an anion that bonds to both the cations. Generally, thesize of atoms of A is larger than the size of B atoms. In someembodiments, the perovskite can be doped (e.g., by La or Lanthanides).In some embodiments, the FE material is perovskite, which includes oneor more of: La, Sr, Co, Sr, Ru, Y, Ba, Cu, Bi, Ca, and Ni. For example,metallic perovskites such as: (La,Sr)CoO₃, SrRuO₃, (La,Sr)MnO₃,YBa₂Cu₃O₇, Bi₂Sr₂CaCu₂O₈, LaNiO₃, BaTiO₃, KNbO₃, NaTaO₃, etc. may beused for the FE material. Perovskites can be suitably doped to achieve aspontaneous distortion in a range of 0.3 to 2%. For example, forchemically substituted lead titanate such as Zr in Ti site; La, Nb in Tisite, the concentration of these substitutes is such that it achievesthe spontaneous distortion in the range of 0.3-2%. For chemicallysubstituted BiFeO3, BrCrO3, BuCoO3 class of materials, La or rare earthsubstitution into the Bi site can tune the spontaneous distortion. Insome embodiments, the FE material is contacted with a conductive metaloxide that includes one of the conducting perovskite metallic oxidesexemplified by: La—Sr—CoO3, SrRuO3, La—Sr—MnO3, YBa2Cu3O7,Bi2Sr2CaCu2O8, and LaNiO3.

In some embodiments, the FE material comprises a stack of layersincluding low voltage FE material between (or sandwiched between)conductive oxides. In various embodiments, when FE material is aperovskite, the conductive oxides are of the type AA′BB′O₃. A′ is adopant for atomic site A, it can be an element from the Lanthanidesseries. B′ is a dopant for atomic site B, it can be an element from thetransition metal elements, especially Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu,Zn. A′ may have the same valency of site A, with a differentferroelectric polarizability. In various embodiments, when metallicperovskite is used for the FE material, conductive oxides can includeone or more of: IrO₂, RuO₂, PdO₂, OsO₂, or ReO₃. In some embodiments,the perovskite is doped with La or Lanthanides. In some embodiments,thin layer (e.g., approximately 10 nm) perovskite template conductorssuch as SrRuO3 coated on top of IrO2, RuO2, PdO2, PtO2, which have anon-perovskite structure but higher conductivity to provide a seed ortemplate for the growth of pure perovskite ferroelectric at lowtemperatures, are used as conductive oxides.

In some embodiments, ferroelectric materials are doped with s-orbitalmaterial (e.g., materials for first period, second period, and ionicthird and fourth periods). In some embodiments, f-orbital materials(e.g., lanthanides) are doped to the ferroelectric material to makeparaelectric material. Examples of room temperature paraelectricmaterials include: SrTiO3, Ba(x)Sr(y)TiO3 (where x is −0.05 or 0.5, andy is 0.95), HfZrO2, Hf—Si—O, La—substituted PbTiO3, PMN-PT based relaxorferroelectrics.

In some embodiments, the FE material comprises one or more of: Hafnium(Hf), Zirconium (Zr), Aluminum (Al), Silicon (Si), their oxides or theiralloyed oxides. In some embodiments, FE material includes one or moreof: Al(1-x)Sc(x)N, Ga(1-x)Sc(x)N, Al(1-x)Y(x)N or Al(1-x-y)Mg(x)Nb(y)N,y doped HfO2, where x includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La,Sc, Si, Sr, Sn, or Y, wherein ‘x’ is a fraction. In some embodiments, FEmaterial includes one or more of: Bismuth ferrite (BFO), lead zirconatetitanate (PZT), BFO with doping material, or PZT with doping material,wherein the doping material is one of Nb or La; and relaxorferroelectrics such as PMN-PT.

In some embodiments, the FE material includes Bismuth ferrite (BFO) witha doping material where in the doping material is one of Lanthanum, orany element from the lanthanide series of the periodic table. In someembodiments, FE material includes lead zirconium titanate (PZT), or PZTwith a doping material, wherein the doping material is one of La, Nb. Insome embodiments, FE material includes a relaxor ferro-electricincluding one of lead magnesium niobate (PMN), lead magnesiumniobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate(PLZT), lead scandium niobate (PSN), Barium Titanium-Bismuth ZincNiobium Tantalum (BT-BZNT), or Barium Titanium-Barium Strontium Titanium(BT-BST).

In some embodiments, the FE material includes Hafnium oxides of theform, Hf1-x Ex Oy where E can be Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si,Sr, Sn, or Y. In some embodiments, the FE material includes Niobate typecompounds LiNbO3, LiTaO3, Lithium iron Tantalum Oxy Fluoride, BariumStrontium Niobate, Sodium Barium Niobate, or Potassium strontiumniobate.

In some embodiments, the FE material comprises multiple layers. Forexample, alternating layers of [Bi2O2]2+, and pseudo-perovskite blocks(Bi4Ti3O12 and related Aurivillius phases), with perovskite layers thatare ‘n’ octahedral layers in thickness can be used. In some embodiments,the FE material comprises organic material. For example, polyvinylidenefluoride or polyvinylidene difluoride (PVDF).

In some embodiments, the FE material comprises hexagonal ferroelectricsof the type h-RMnO3, where R is a rare earth element viz. cerium (Ce),dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium(Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr),promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium(Tm), ytterbium (Yb), and yttrium (Y). The ferroelectric phase ischaracterized by a buckling of the layered MnO5 polyhedra, accompaniedby displacements of the Y ions, which lead to a net electricpolarization. In some embodiments, hexagonal FE includes one of: YMnO3or LuFeO3. In various embodiments, when the FE material compriseshexagonal ferroelectrics, the conductive oxides are of A2O3 (e.g.,In2O3, Fe2O3) and ABO3 type, where ‘A’ is a rare earth element and B isMn.

In some embodiments, the FE material comprises improper FE material. Animproper ferroelectric is a ferroelectric where the primary orderparameter is an order mechanism such as strain or buckling of the atomicorder. Examples of improper FE material are LuFeO3 class of materials orsuper lattice of ferroelectric and paraelectric materials PbTiO3 (PTO)and SnTiO3 (STO), respectively, and LaAlO3 (LAO) and STO, respectively.For example, a super lattice of [PTO/STO]n or [LAO/STO]n, where ‘n’ isbetween 1 to 100. In some embodiments, the paraelectric materialincludes one of: SrTiO3, Ba(x)Sr(y)TiO3 (where x is −0.5, and y is0.95), BaTiO3, HfZrO2, Hf—Si—O, La-substituted PbTiO3, or PMN-PT basedrelaxor ferroelectrics.

FIG. 2A illustrates 2-input consensus element (c-element) 200 comprisinga 3-input minority gate and an inverter, where an adjustable thresholdgate is programmed as a 3-input minority gate, in accordance with someembodiments. In some embodiments, c-element 200 comprises 3-inputminority gate 201 and inverter 202. Inputs to 3-input minority gate 201are in1, in2, and output “out” of inverter 202. Input in1 is connectedto input pin 1, input in2 is connected to input pin 2, and output “out”(which is the third input in3) is connected to input pin 3. Output (o)of 3-input minority gate 201 is provided to node n1 which is input toinverter 202.

In various embodiments, c-element 200 outputs on node “out” a consensusof inputs in1 and in2. For example, when inputs in1 and in2 are alllogic 1, then the output “out” of c-element 200 is logic 1, and wheninputs in1 and in2 are all logic 0, then the output “out” of thec-element 200 is logic 0.

In some embodiments, the output is state-holding when all inputs (e.g.,in1 and in2) are not the same logic value. For example, a 3-inputc-element is state holding when all three inputs are not the samelogical value. In this case the output will be the output from aprevious state (e.g., holding logic 0 or 1 from a previous state). Invarious embodiments, 3-input minority gate 201 is implemented as aninverted threshold gate which is configured or programmed to have athreshold of 2 to implement a minority gate. The inverted threshold gateis a capacitive input circuit where capacitors can have lineardielectric, paraelectric dielectric or ferroelectric dielectric, inaccordance with various embodiments.

FIG. 2B illustrates 3-input c-element 220 comprising a 5-input minoritygate and an inverter, where an adjustable threshold gate is programmedas a 5-input minority gate, in accordance with some embodiments. In someembodiments, c-element 220 comprises 5-input minority gate 221 andinverter 202. Inputs to 5-input minority gate 221 are in1, in2, in3, andoutput “out” of inverter 202. Output of 5-input minority gate 221 isprovided to node n1 which is input to inverter 202. Two of the inputs(inputs ‘4’ and ‘5’) of 5-input minority gate 221 are connected to node“out”. In some embodiments, input in1 is connected to input pin 1, inputin2 is connected to input pin 2, input in3 is connected to input pin 3,output “out” (which is the fourth input in4) is connected to input pin4, and output “out” (which is the fifth input in5) is connected to inputpin 5.

In various embodiments, c-element 220 outputs on node “out” a consensusof inputs in1, in2, and in3. For example, when inputs in1, in2, and in3are all logic 1, then the output “out” of c-element 220 is logic 1, andwhen inputs in1, in2, and in3 are all logic 0, then the output “out” ofthe c-element 220 is logic 0. In some embodiments, the output “out” isstate-holding when one of the inputs (e.g., one of in1, in2, or in3) isa logic 1 and one of the inputs (e.g., one of in1, in2, or in3) is alogic 0. The output is state-holding when all inputs are not the samelogic value. In various embodiments, 5-input minority gate 221 isimplemented as an inverted threshold gate which is configured orprogrammed to have a threshold of 3 to implement a minority gate. Insome embodiments, the inverted threshold gate is a capacitive inputcircuit where capacitors can have linear dielectric, paraelectricdielectric or ferroelectric dielectric. While the embodiments hereillustrate a 2-input c-element and a 3-input c-element, other number ofinputs can be used too. In one such embodiment, the threshold of thecapacitive input circuits can be adjusted to perform a desired functionaccording to the number of inputs of the c-element.

FIG. 3A illustrates 2-input c-element 300 comprising a 3-input majoritygate, where an adjustable threshold gate is programmed as a 3-inputmajority gate, in accordance with some embodiments. 2-input c-element300 is like 2-input c-element 200 but without inverter 202 and 3-inputminority gate replaced with a 3-input majority gate. In someembodiments, inputs to 3-input majority gate 301 are in1, in2, andoutput “out”. Input in1 is connected to input pin 1, input in2 isconnected to input pin 2, and output “out” (which is the third inputin3) is connected to input pin 3. In various embodiments, c-element 300outputs on node “out” a consensus of inputs in1 and in2. For example,when inputs in1 and in2 are all logic 1, then the output “out” ofc-element 300 is logic 1, and when inputs in1 and in2 are all logic 0,then the output “out” of the c-element 300 is logic 0. In someembodiments, the output “out” is state-holding when one of the inputs(e.g., one of in1 or in2) is a logic 1 and one of the inputs (e.g., oneof in1 or in2) is a logic 0. The output is state-holding when all inputsare not the same logic value

In various embodiments, 3-input majority gate 301 is implemented as athreshold gate which is configured or programmed to have a threshold of2 to implement a majority gate. In some embodiments, the threshold gateis a capacitive input circuit where capacitors can have lineardielectric, paraelectric dielectric or ferroelectric dielectric.

FIG. 3B illustrates 3-input c-element 320 comprising a 5-input majoritygate, where an adjustable threshold gate is programmed as a 5-inputmajority gate, in accordance with some embodiments. Inputs to 5-inputmajority gate 321 are in1, in2, in3, and output “out”. Two of the inputsof 5-input majority gate 321 are connected to node “out”. In someembodiments, input in1 is connected to input pin 1, input in2 isconnected to input pin 2, input in3 is connected to input pin 3, output“out” (which is the fourth input in4) is connected to input pin 4, andoutput “out” (which is the fifth input in5) is connected to input pin 5.

In various embodiments, c-element 320 outputs on node “out” a consensusof inputs in1, in2, and in3. For example, when inputs in1, in2, and in3are all logic 1, then the output “out” of c-element 320 is logic 1, andwhen inputs in1, in2, and in3 are all logic 0, then the output “out” ofthe c-element 320 is logic 0. In some embodiments, the output “out” isstate-holding when one of the inputs (e.g., one of in1, in2, or in3 ) isa logic 1 and one of the inputs (e.g., one of in1, in2, or in3 ) is alogic 0. The output is state-holding when all the inputs are not thesame logic value. In various embodiments, 5-input majority gate 321 isimplemented as a threshold gate which is configured or programed to havea threshold of 3 to implement a majority gate. In some embodiments, thethreshold gate is a capacitive input circuit where capacitors can havelinear dielectric, paraelectric dielectric or ferroelectric dielectric.

FIG. 4 illustrates 8-input completion tree 400 comprising c-elements, inaccordance with some embodiments. In various embodiments, 8-inputcompletion tree 400 is a network or tree of c-elements (e.g., c-elements200, 220, 300, 320). The output of the completion tree is a logic 1 whenall inputs to the completion tree are logic 1, in accordance with someembodiments. The output of the completion tree is a logic 0 when allinputs to the completion tree are a logic 0, in accordance with someembodiments. The output of the completion tree is state-holding when theinputs have at least one input having logic 1 and one input having logic0. The output is state-holding when all the inputs are not the samelogic value.

In some embodiments, 8-input completion tree 400 comprises c-elements401, 402, 403, 404, 405, 406, and 407. In some embodiments, c-element401 receives inputs in1 and in2 and generates an output of which isindicative of a consensus of inputs in1 and in2. In some embodiments,c-element 402 receives inputs in3 and in4 and generates an output o2which is indicative of a consensus of inputs in3 and in4. In someembodiments, c-element 403 receives outputs o1 and o2 and generates anoutput o5 which is a consensus of outputs o1 and o2. In someembodiments, c-element 404 receives inputs in5 and in6 and generates anoutput o3 which is indicative of a consensus of inputs in5 and in6. Insome embodiments, c-element 405 receives inputs in7 and in8 andgenerates an output o4 which is indicative of a consensus of inputs in7and in8. In some embodiments, c-element 406 receives outputs o3 and o4and generates an output o6 which is a consensus of outputs o3 and o4. Insome embodiments, c-element 407 receives outputs o5 and o6 and generatesa final output which is a consensus of outputs o5 and o6. The c-elementsof the completion tree can be implemented according to any of c-elementimplementations discussed herein.

FIG. 5 illustrates 16-input completion tree 500 comprising the 8-inputcompletion trees and a c-element, in accordance with some embodiments.16-input completion tree 500 provides an example of how an N-inputcompletion tree can be constructed. In some embodiments, 16-inputcompletion tree 500 comprises first 8-input completion tree 501, second8-input completion tree 502, and 2-input c-element 503. In someembodiments, first 8-input completion tree 501 and second 8-inputcompletion tree 502 is according to 8-input completion tree 400.

In some embodiments, 8-input completion tree 501 receives a first set ofeight inputs in1, in2, in3, in4, in5, in6, in7, and in8, and generatesan output o1 which indicates a completion function of a first set ofeight inputs. For example, output o1 is 1 when all inputs in1, in2, in3,in4, in5, in6, in7, and in8 are logic 1. Output o1 is 0 when all inputsin1, in2, in3, in4, in5, in6, in7, and in8 are logic 0. Output o1 holdsits logic state when at least one input and at least one output to8-input completion tree 501 is a logic 1 and a logic 0. In someembodiments, 8-input completion tree 502 receives a second set of eightinputs in9, in10, in11, in12, in13, in14, in15, and in16, and generatesan output o1 which indicates a completion function of the second set ofeight inputs. For example, output o2 is 1 when all inputs in9, in10,in11, in12, in13, in14, in15, and in16 are logic 1. Output o1 is 0 whenall inputs in9, in10, in11, in12, in13, in14, in15, and in16 are logic0. Output o1 holds its logic state when at least one input and at leastone output to 8-input completion tree 502 is a logic 1 and a logic 0. Invarious embodiments, 2-input c-element 503 receives outputs o1 and o2and generates Output which indicates a consensus of outputs o1 and o2.2-input c-element 503 can be any of one of c-elements 200, 220, 300,320. While the various illustrate two examples of completion tree, theconcept can be applied to an N-input completion tree.

FIG. 6 illustrates 8-input validity tree 600 comprising OR gates andc-elements, in accordance with some embodiments. In some embodiments,8-input validity tree 600 comprises OR gates 601, 602, 603, and 604, andc-elements 403, 406, and 407. In some embodiments, 8-input validity tree600 is like 8-input completion tree 600 but for OR gates that replacec-elements 401, 402, 404, and 405.

In some embodiments, OR gates receive the inputs. For example, OR gate601 receives inputs in1 and in2 and generates output o1 which is an ORfunction of inputs in1 and in2. In some embodiments, OR gate 602receives inputs in3 and in4 and generates output o2 which is an ORfunction of inputs in3 and in4. In some embodiments, OR gate 603receives inputs in5 and in6 and generates output o3 which is an ORfunction of inputs in5 and in6. In some embodiments, OR gate 604receives inputs in7 and in8 and generates output o4 which is an ORfunction of inputs in7 and in8. The outputs of the OR gates are input tothe c-elements.

In some embodiments, c-element 403 receives outputs o1 and o2 andgenerates an output o5 which is a consensus of outputs o1 and o2. Insome embodiments, c-element 406 receives outputs o3 and o4 and generatesan output o6 which is a consensus of outputs o3 and o4. In someembodiments, c-element 407 receives outputs o5 and o6 and generates afinal output which is a consensus of outputs o5 and o6.

In some embodiments, the OR gates are implemented as threshold gateswhose threshold is programmed or adjusted to generate an OR function. Insome embodiments, the output of 8-input validity tree 600 is logic 1when all input bits are valid, in accordance with some embodiments. Theoutput of 8-input validity tree 600 is logic 0 when all input bits areneutral. When the inputs bits are either valid or neutral, the output of8-input validity tree 600 holds its state, in accordance with someembodiments. In various embodiments, an individual input comprises twobits, ‘f’ and ‘t’. For example, a data input channel X includes a firstbit X.f and a second bit X.t. In this example, would in1 be X.f and in2be X.t. An individual input X has a valid 0 state if X.f is logic 1 andif X.t is logic 0, in accordance with some embodiments. An individualinput X has a valid 1 state if X.f is logic 0 and if X.t is logic 1, inaccordance with some embodiments. An individual input X has a neutralstate if X.f is logic 0 and if X.t is logic 0, in accordance with someembodiments.

FIG. 7 illustrates 16-input validity tree 700 comprising the 8-inputvalidity trees and a c-element, in accordance with some embodiments. Insome embodiments, 16-input completion tree 700 comprises first 8-inputvalidity tree 701, second 8-input validity tree 702, and 2-inputc-element 703. In some embodiments, first 8-input validity tree 701 andsecond 8-input validity tree 702 is according to 8-input validity tree600.

In some embodiments, 8-input completion tree 701 receives a first set ofeight inputs in1, in2, in3, in4, in5, in6, in7, and in8, and generatesan output o1 which indicates a validity function of the first set ofeight inputs. In some embodiments, 8-input completion tree 702 receivesa second set of eight inputs in9, in10, in11, in12, in13, in14, in15,and in16, and generates an output o1 which indicates a validity functionof the first set of eight inputs. In various embodiments, 2-inputc-element 703 receives outputs o1 and o2 and generates Output whichindicates a consensus of outputs o1 and o2. 2-input c-element 703 can beany of one of c-elements 200, 220, 300, 320. While the variousillustrate two examples of validity tree, the concept can be applied toan N-input validity tree.

The following section describes various embodiments of adjustablethreshold gate that can be used as basis for the c-element, completiontree, and/or validity tree, in accordance with various embodiments.

FIG. 8A illustrates a 2-input adjustable threshold gate 800 with linearor paraelectric capacitors and a pull-up device on a summing node, inaccordance with some embodiments. In some embodiments, 2-inputcapacitive circuit 800 comprises a first input (a), a second input (b),summing node (n1), first capacitor C1, second capacitor C2,pull-up-device MP1, driver 801, and output (out) coupled as shown. Insome embodiments, the first capacitor C1 includes a first terminalcoupled to the first input and a second terminal coupled to the summingnode n1. In some embodiments, the second capacitor C2 includes a thirdterminal coupled to the second input and a fourth terminal coupled tothe summing node n1. In some embodiments, the pull-up device MP1 iscoupled to the summing node n1 and a power supply rail Vdd, wherein thepull-up device MP1 is controlled by a first control (up).

In various embodiments, during the reset phase, node n1 is pulled-up bytransistor MP1 to Vdd, and inputs ‘a’ and ‘b’ are conditioned viaconditioning circuit 802 to adjust the threshold of 2-input capacitivecircuit 800. Conditioning circuitry 802 may receive inputs in1 and in2,and configuration setting (e.g., reset or evaluation) to determine theoutputs ‘a’, ‘b’, and control “up”. During the evaluation phase, in1 ispassed on to output ‘a’ and in2 is passed on to ‘b’. During the resetphase, depending on a desired threshold, outputs ‘a’ and ‘b’ areconditioned.

Here the term threshold generally refers to a number that indicates anumber of inputs that should be set to logic high to perform a functionof a threshold gate. For instance, by turning on/off the pull-up deviceMP1 and conditioning the inputs ‘a’ and ‘b’ during a reset phase, thecharge at node n1 is set so that in an evaluation phase when the pull-updevice MP1 is disabled, the input capacitive circuit attains a desiredfunction. In one instance, when the threshold is set to 2 in a resetphase by a particular sequencing of turning on/off the pull-up deviceand conditioning of the inputs ‘a’ and ‘b; it means that during anevaluation phase when both inputs ‘a’ and ‘b’ are logic high, thenvoltage on node n1 is logic high. Continuing with this example, when anyof the inputs ‘a’ and ‘b’ is a logic low, then the voltage on node n1resolves to logic low. As such, 2-input capacitive circuit 800 isprogrammed or configured as a AND gate at node n1 and a NAND gate atoutput out.

Likewise, when the threshold is set to 1 in a reset phase by aparticular sequencing of turning on/off the pull-up device andconditioning of the inputs ‘a’ and ‘b; it means that during anevaluation phase when either input ‘a’ and ‘b’ is logic high, thenvoltage on node n1 is logic high. Continuing with this example, whenboth the inputs ‘a’ and ‘b’ are a logic low, then the voltage on node n1resolves to logic low. As such, 2-input capacitive circuit 800 isprogrammed or configured as an OR gate at node n1 and a NOR gate atoutput out. So, the same circuit can be used as a AND/NAND or OR/NORgate by conditioning the inputs and resetting or setting the voltage onthe summing node during a reset phase. Subsequently, in the evaluationphase the circuit will behave as AND/NAND or OR/NOR gate.

In some embodiments, conditioning circuitry 802 turns off the pull-updevice MP1 during an evaluation phase separate from the reset phase. Thereset phase or evaluation phase are indicated by the logic level ofConfig. For example, conditioning circuitry 802 sets the first control(up) to logic high (Vdd) and the second control (down) to logic low(ground) during an evaluation phase (e.g., Config is set to logic 1).Likewise, in a reset phase, Config is set to 0. This is just an example,and the logic level of Config can be modified to present the evaluationphase and the reset phase.

Table 1 illustrates that when inputs ‘a’ and ‘b’ are conditioned aslogic 1 and pull-up device MP1 is enabled during the reset phase, thenthe threshold is set to 1. In the evaluation phase, 2-input capacitivecircuit 800 can then behave as a NOR gate. Here, the capacitors compriselinear dielectric. Note, this example assumes equal weights (orsubstantially equal) for C1 and C2 (e.g., C1=C2). In some embodiments,the threshold may change (e.g., from 1 to 2) when the ratio ofcapacitances of capacitors C1 and C2 are modified.

TABLE 1 Input ‘a’ Input ‘b’ First control (Up) Threshold 0 0 0 (enableMP1) 0 1 0 0 (enable MP1) 0 1 1 0 (enable MP1) 1

A threshold of 0 means that the capacitive-input circuit is an always oncircuit regardless of the logic levels of the inputs. In one suchembodiment, during the evaluation phase for the circuit configured withthreshold of zero, the logic value on node n1 is logic 1, and the logicvalue on output out is logic 0 (assuming the driver is an inverter).

When the capacitors comprise paraelectric material, different thresholdsare achieved compared to the linear dielectric material for the sameinput conditioning.

Table 2 illustrates that when inputs ‘a’ and ‘b’ are conditioned aslogic 1 and pull-up device MP1 is enabled during the reset phase, thenthe threshold is set to 1. In the evaluation phase, 2-input capacitivecircuit 800 can then behave as a NOR gate. In some embodiments, wheninputs ‘a’ and ‘b’ are conditioned as logic 1 and logic 0, respectively,and pull-up device MP1 is enabled during the reset phase, then thethreshold is set to 1. In the evaluation phase, 2-input capacitivecircuit 800 can then behave as an OR/NOR gate when the threshold is setto 1. In some embodiments, when inputs ‘a’ and ‘b’ are conditioned aslogic 0 and pull-up device MP1 is enabled during the reset phase, thenthe threshold is set to 0. Note, this example assumes equal weights (orsubstantially equal) for C1 and C2 (e.g., C1=C2). In some embodiments,the threshold may change (e.g., from 1 to 2 or to some other level) whenthe ratio of capacitances of capacitors C1 and C2 are modified. Table 2is the case when capacitors are paraelectric capacitors.

TABLE 2 Input ‘a’ Input ‘b’ First control (Up) Threshold 0 0 0 (enableMP1) 0 1 0 0 (enable MP1) 1 1 1 0 (enable MP1) 1

While the embodiment of FIG. 8A illustrates an inverter as driver 801,driver 801 can be any suitable logic. In some embodiments, driver 801 isa non-inverting circuit such as a buffer, AND, OR, a capacitive inputcircuit, or any non-inverting circuit. In some embodiments, driver 801is an inverting circuit such as an inverter, NAND, NOR, XOR, XNOR, orany inverting circuit etc. In some embodiments, driver 801 is amultiplexer that connects summing nodes of other capacitive circuits toits inputs. In some embodiments, one or more inputs of the multiplexerare driven from a transistor-based logic. As such, the multiplexer canselectively output a desired output. In some embodiments, driver 801 isanother capacitive input circuit where one of the inputs is coupled tothe summing node n1 and other input(s) are coupled to other inputs. Assuch, complex logic can be formed with configurable threshold and thusfunction(s).

FIG. 8B illustrates 2-input adjustable threshold gate 820 with linear orparaelectric capacitors and a pull-down device on a summing node, inaccordance with some embodiments. Compared to FIG. 8A, here pull-updevice MP1 is removed and replaced with a pull-down device MN1 coupledto summing node n1 and ground supply terminal.

In various embodiments, during the reset phase, node n1 is pulled-downby transistor MN1 to ground, and inputs ‘a’ and ‘b’ are conditioned viaconditioning circuit 822 to adjust the threshold of 2-input capacitivecircuit 820. Table 3 illustrates input conditioning that provides athreshold of 2 when capacitors are linear capacitors. Conditioningcircuitry 822 may receive inputs in1 and in2, and configuration setting(e.g., reset or evaluation) to determine the outputs ‘a’, ‘b’, and down.During the evaluation phase, in1 is passed on to output ‘a’ and in2 ispassed on to ‘b’. During the reset phase, depending on a desiredthreshold, outputs ‘a’ and ‘b’ are conditioned.

TABLE 3 Input ‘a’ Input ‘b’ Second control (down) Threshold 0 0 1(enable MN1) 2 1 0 1 (enable MN1) 2 1 1 1 (enable MN1) 2

In this case, when inputs ‘a’ and ‘b’ are conditioned as shown in Table3 and pull-down device MN1 is enabled during the reset phase, then thethreshold is set to 2. In the evaluation phase, 2-input capacitivecircuit 820 can then behave as an NAND gate. Note, this example assumesequal weights for C1 and C2 (e.g., C1=C2). In some embodiments, thethreshold may change (e.g., from 2 to 1) when the ratio of capacitancesof capacitors C1 and C2 are modified.

Table 4 illustrates input conditioning that provides a threshold of 2.When the capacitors comprise paraelectric material, different thresholdsare achieved compared to the linear dielectric material for the sameinput conditioning. Table 4 is the case when capacitors compriseparaelectric material.

Conditioning circuitry 822 may receive inputs in1 and in2, andconfiguration setting (e.g., reset or evaluation) to determine theoutputs ‘a’, ‘b’, and down. During the evaluation phase, in1 is passedon to output ‘a’ and in2 is passed on to ‘b’. During the reset phase,depending on a desired threshold, outputs ‘a’ and ‘b’ are conditioned.

TABLE 4 Input ‘a’ Input ‘b’ Second control (down) Threshold 0 0 1(enable MN1) 2 1 0 1 (enable MN1) 2 1 1 1 (enable MN1) 3

In this case, when inputs ‘a’ and ‘b’ are conditioned as shown in Table4 and pull-down device MN1 is enabled during the reset phase, then thethreshold is set to 2. In the evaluation phase, 2-input capacitivecircuit 820 can then behave as an AND or NAND gate. In some embodiments,when inputs ‘a’ and ‘b’ are conditioned as logic 1 and pull-down deviceMN1 is enabled during the reset phase, then the threshold is set to 3.In the evaluation phase, when the threshold is higher than the number ofinputs, 2-input capacitive circuit 820 behaves as a disconnected circuitwhere internal node n1 is floating and the output of driver out may be adon't care logic value. Note, this example assumes equal weights for C1and C2 (e.g., C1=C2). In some embodiments, the threshold may change(e.g., from 2 to 1) when the ratio of capacitances of capacitors C1 andC2 are modified.

While the embodiments are illustrated with reference to samecapacitances for first capacitor C1 and the second capacitor C2, thethreshold can be affected by changing the capacitive ratio of C1 and C2.For example, the input conditioning scheme and the pull-up and pull-downdevice control can result in a different threshold than that in Table 4when the capacitive ratio of C1 and C2 is not 1:1. Overall, theconfiguring scheme of various embodiments herein provide the flexibilityof programming the threshold for 2-input capacitive circuit 820 in areset phase to achieve a certain logic function in the evaluation phase.

FIG. 9A illustrates 3-input adjustable threshold gate 900 with linear orparaelectric capacitors and a pull-up device on a summing node, inaccordance with some embodiments. 3-input capacitive circuit 900 is like2-input capacitive circuit 800 but for additional input ‘c’ andassociated capacitor C3. In some embodiments, a first terminal ofcapacitor C3 is coupled to input ‘c’ while a second terminal ofcapacitor C3 is coupled to summing node n1. Conditioning circuit 902 isreplaced with a conditioning circuit 902. Conditioning circuitry 902 mayreceive inputs in1, in2, and in3 and configuration setting (e.g., resetor evaluation) to determine the outputs ‘a’, ‘13’, ‘c’, and up. Duringthe evaluation phase, in1 is passed on to output ‘a’, in2 is passed onto ‘b’, and in3 is passed on to ‘c’. During the reset phase, dependingon a desired threshold, outputs ‘a’, ‘b’, and ‘c’ are conditioned.

In some embodiments, by turning on/off the pull-up device MP1 andconditioning the inputs ‘a’, ‘b’, and ‘c’ during a reset phase, thecharge at node n1 is set so that in an evaluation phase when the pull-updevice is disabled, 3-input capacitive circuit 900 attains a desiredfunction.

In one instance, when the threshold is set to 2 in a reset phase by aparticular sequencing of turning on/off the pull-up device andconditioning of the inputs ‘a’, ‘b’, and ‘c’; it means that during anevaluation phase when at least two of the three inputs ‘a’, ‘b’, and ‘c’are logic high, then voltage on node n1 is logic high. Continuing withthis example, when at least two inputs of the three inputs ‘a″b’, and‘c’ is a logic low, then the voltage on node n1 resolves to logic low.As such, 3-input capacitive circuit 900 is programmed or configured as amajority gate at node n1 and a minority gate at output out (when thedriver circuitry is an inverter). In some cases, depending upon theleakage balance of pull-up transistor MP1 as it impacts charge on thesumming node n1, 3-input capacitive circuit 900 may lose its majoritylogic functionality over time. This loss in functionality of themajority function can be restored by resetting the summing node n1 viatransistor MP1, in accordance with some embodiments.

In some embodiments, when the threshold is set to 3 in a reset phase bya particular sequencing of turning on/off the pull-up device andconditioning of the inputs ‘a’, ‘b’, and ‘c’; it means that during anevaluation phase when all three inputs ‘a’, ‘b’, and ‘c’ are logic high,then voltage on node n1 is logic high. Continuing with this example,when any of the three inputs ‘a″b’, and ‘c’ is a logic low, then thevoltage on node n1 resolves to logic low. As such, 3-input capacitivecircuit 900 is programmed or configured as a 3-input AND at node n1 anda 3-input NAND gate at output out (assuming the driver circuitry is aninverter).

In some embodiments, when the threshold is set to 1 in a reset phase bya particular sequencing of turning on/off the pull-up device andconditioning of the inputs ‘a’ and ‘b; it means that during anevaluation phase when any of the inputs ‘a’ ‘b’, or ‘c’ is logic high,then voltage on node n1 is logic high. Continuing with this example,when all inputs ‘a’, ‘b’, or ‘c’ is a logic low, then the voltage onnode n1 resolves to logic low. As such, 3-input capacitive circuit 900is programmed or configured as an OR gate at node n1 and a NOR gate atoutput out.

So, the same circuit can be used as a majority/minority gate, AND/NANDor OR/NOR gate by conditioning the inputs and resetting or setting thevoltage on the summing node during a reset phase. Subsequently, in theevaluation phase the circuit will behave as a 3-input majority/minority,3-input AND/NAND or 3-input OR/NOR gate.

In some embodiments, conditioning circuitry 902 sets the threshold to 0in a reset phase by enabling the pull-up device MP1 and providing logic1 to the first input ‘a’, logic 0 to the second input ‘b’, and logic 0to the third input ‘c’. In some embodiments, conditioning circuitry 902sets the threshold to 0 in a reset phase by turning on or enabling thepull-up device MP1 and providing logic 0 to all inputs ‘a’, ‘b’, and‘c’. A threshold of 0 means that the capacitive-input circuit is analways on circuit regardless of the logic levels of inputs. In one suchembodiment, during the evaluation phase for the circuit configured withthreshold of zero, the logic value on node n1 is logic 1, and the logicvalue on output out is logic 0 (assuming the driver is an inverter).

In some embodiments, conditioning circuitry 902 (or any otherconditioning circuit) sets the threshold to 4. A threshold of 4 for a3-input capacitive circuit means that capacitive input circuit is analways off circuit regardless of the logic levels of the inputs. In onesuch embodiment, during the evaluation phase for the circuit configuredwith threshold of n+1 (e.g., 4, where ‘n’ is the number of capacitiveinputs), the logic value on node n1 is floating and may eventuallydischarge to ground or charge to supply level. In some embodiments, thevoltage on node n1 is zero volts regarding of input setting when thethreshold in 4 (e.g., n+1).

Table 5 illustrates that when inputs ‘a’, ‘b’, and ‘c’ are conditionedand pull-up device MP1 is enabled during the reset phase, then thethreshold is set to 0, 1, or 2. In this example, the capacitors compriselinear dielectric.

TABLE 5 ‘a’ ‘b’ ‘c’ First control (Up) Threshold 0 0 0 0 (enable MP1) 01 0 0 0 (enable MP1) 0 1 1 0 0 (enable MP1) 1 1 1 1 0 (enable MP1) 2

In the evaluation phase, 3-input capacitive circuit 900 can then behaveas an OR/NOR gate (when threshold is 1) or a majority/minority gate(when threshold is 2). Note, this example assumes equal weights for C1,C2, and C3 (e.g., C1=C2=C3). In some embodiments, the threshold maychange (e.g., from 1 to 2) when the ratio of capacitances of capacitorsC1, C2, and/or C3 are modified.

Table 6 illustrates that when inputs ‘a’, ‘b’, and ‘c’ are conditionedand pull-up device MP1 is enabled during the reset phase, then thethreshold is set to 0, 1, or 2. When the capacitors compriseparaelectric material, different thresholds are achieved compared to thelinear dielectric material for the same input conditioning. Table 6 isthe case when capacitors comprise paraelectric material.

TABLE 6 ‘a’ ‘b’ ‘c’ First control (Up) Threshold 0 0 0 0 (enable MP1) 01 0 0 0 (enable MP1) 1 1 1 0 0 (enable MP1) 1 1 1 1 0 (enable MP1) 2

In the evaluation phase, 3-input capacitive circuit 900 can then behaveas a logic1/logic0 driver (when threshold is 0), an OR/NOR gate (whenthreshold is 1), a minority/minority gate (when threshold is 2). Note,this example assumes equal weights for C1, C2, and C3 (e.g., C1=C2=C3).In some embodiments, the threshold may change (e.g., from 1 to 2 or toanother other value) when the ratio of capacitances of capacitors C1,C2, and/or C3 are modified.

FIG. 9B illustrates a 3-input adjustable threshold gate 920 with linearor paraelectric capacitors and a pull-down device on a summing node, inaccordance with some embodiments. Compared to FIG. 9A, here the pull-updevice MP1 is removed and pull-down device MN1 is added which is coupledto node n1 and ground supply rail. In various embodiments, during thereset phase, node n1 is pulled-down by MN1 to ground, and inputs ‘a’,‘b’, and ‘c’ are conditioned via configuration circuit 922 to adjust thethreshold of 3-input capacitive circuit 920. Conditioning circuitry 922may receive inputs in1, in2, and in3 and configuration setting(s) (e.g.,reset or evaluation) to determine the outputs ‘a’, ‘b’, ‘c’, and down.During the evaluation phase, in1 is passed on to output ‘a’, in2 ispassed on to ‘b’, and in3 is passed on to ‘c’. During the reset phase,depending on a desired threshold, outputs ‘a’, ‘b’, and ‘c’ areconditioned. Table 7 illustrates that when inputs ‘a’, ‘b’, and ‘c’ areconditioned and pull-down device MN1 is enabled during the reset phase,then the threshold is set to 2 or 3. In this example, the capacitorscomprise linear dielectric material.

TABLE 7 ‘a’ ‘b’ ‘c’ Second control (down) Threshold 0 0 0 1 (enable MN1)2 1 0 0 1 (enable MN1) 3 1 1 0 1 (enable MN1) 3 1 1 1 1 (enable MN1) 3

In the evaluation phase, 3-input capacitive circuit 920 can then behaveas a majority/majority gate (when threshold is 2) or an AND/NAND gate(when threshold is 3). Note, this example assumes equal weights for C1,C2, and C3 (e.g., C1=C2=C3). In some embodiments, the threshold maychange (e.g., from 3 to 2 or to 1) when the ratio of capacitances ofcapacitors C1, C2, and/or C3 are modified.

Table 8 illustrates that when inputs ‘a’, ‘b’, and ‘c’ are conditionedand pull-down device MN1 is enabled during the reset phase, then thethreshold is set to 2, 3, or 4. When the capacitors compriseparaelectric material, different thresholds are achieved compared to thelinear dielectric material for the same input conditioning. Table 8 isthe case when capacitors comprise paraelectric material.

TABLE 8 ‘a’ ‘b’ ‘c’ Second control (down) Threshold 0 0 0 1 (enable MN1)2 1 0 0 1 (enable MN1) 3 1 1 0 1 (enable MN1) 3 1 1 1 1 (enable MN1) 4

In the evaluation phase, 3-input capacitive circuit 920 can then behaveas a logic1/logic0 driver (when threshold is 0), a majority/majoritygate (when threshold is 2), an AND/NAND gate (when threshold is 3), or adisconnected circuit (when threshold is 4). Note, this example assumesequal weights for C1, C2, and C3 (e.g., C1=C2=C3). In some embodiments,the threshold may change (e.g., from 3 to 2 or to 1, or any other value)when the ratio of capacitances of capacitors C1, C2 and/or C3 aremodified.

FIG. 10A illustrates 5-input adjustable threshold gate 1000 with linearor paraelectric capacitors and a pull-up device on a summing node, inaccordance with some embodiments. FIG. 10A is comparable to FIG. 9A, butfor additional input ‘d’ and associated capacitor C4 and additionalinput ‘e’ and associated capacitor C5. In some embodiments, a firstterminal of capacitor C4 is coupled to input ‘d’ while a second terminalof capacitor C4 is coupled to summing node n1. In some embodiments, afirst terminal of capacitor C5 is coupled to input ‘e’ while a secondterminal of capacitor C5 is coupled to summing node n1. Conditioningcircuit 902 is replaced with a conditioning circuit 1002. Conditioningcircuitry 1002 may receive inputs in1, in2, in3, in4, and in5 andconfiguration setting (e.g., reset or evaluation) to determine theoutputs ‘a’, ‘b’, ‘c’, ‘d’, ‘e’, and control “up”. During the evaluationphase, in1 is passed on to output ‘a’, in2 is passed on to ‘b’, in3 ispassed on to ‘c’, in4 is passed on to ‘d’, and in5 is passed on to ‘e’.During the reset phase, depending on a desired threshold, outputs ‘a’,‘b’, ‘c’ ‘d’, and ‘e’ are conditioned.

In various embodiments, during the reset phase, node n1 is pulled-up byMP1 to Vdd, and inputs ‘a’, ‘b’, ‘c’, ‘d’, and ‘e’ are conditioned viaconfiguration circuitry 1002 to adjust the threshold of 5-inputcapacitive circuit 1000. Conditioning circuitry 1002 may receive inputsin1, in2, in3, in4, and in5 and configuration setting (e.g., reset orevaluation) to determine the outputs ‘a’, ‘b’, ‘c’, ‘d’, ‘e’, andcontrol “up”. During the evaluation phase, in1 is passed on to output‘a’, in2 is passed on to ‘b’, in3 is passed on to ‘c’, in4 is passed onto ‘d’, and in5 is passed on to ‘e’. During the reset phase, dependingon a desired threshold, outputs ‘a’, ‘b’, ‘c’ ‘d’, and ‘e’ areconditioned. Table 9 illustrates that when inputs ‘a’, ‘b’, ‘c’, ‘d’,and ‘e’ are conditioned and pull-up device MP1 is enabled during thereset phase, then the threshold is set to 1 or 3. In this example, thecapacitors comprise linear dielectric material.

TABLE 9 ‘a’ ‘b’ ‘c’ ‘d’ ‘e’ First control (Up) Threshold 0 0 0 0 0 0(enable MP1) 0 1 0 0 0 0 0 (enable MP1) 0 1 1 0 0 0 0 (enable MP1) 0 1 11 0 0 0 (enable MP1) 1 1 1 1 1 0 0 (enable MP1) 2 1 1 1 1 1 0 (enableMP1) 3

In the evaluation phase, 5-input capacitive circuit 1000 can then behaveas an OR/NOR gate (when threshold is 1), a majority-0/minority-0 gate(when threshold is 2), or a majority/minority gate (when threshold is3). Note, this example assumes equal weights for C1, C2, C3, C4, and C5(e.g., C1=C2=C3=C4=C5). In some embodiments, the threshold may change(e.g., from 1 to 2 or to 3, 4, or 5) when the ratio of capacitances ofcapacitors C1, C2, C3, C4, and/or C5 are modified.

Table 10 illustrates that when inputs ‘a’, ‘13’, ‘c’, ‘d’, and ‘e’ areconditioned and the pull-up device MP1 is enabled during the resetphase, then the threshold is set to 1 or 3. When the capacitors compriseparaelectric material, different thresholds are achieved compared to thelinear dielectric material for the same input conditioning. Table 10 isthe case when capacitors comprise paraelectric material.

TABLE 10 ‘a’ ‘b’ ‘c’ ‘d’ ‘e’ First control (Up) Threshold 0 0 0 0 0 0(enable MP1) 0 1 0 0 0 0 0 (enable MP1) 1 1 1 0 0 0 0 (enable MP1) 1 1 11 0 0 0 (enable MP1) 2 1 1 1 1 0 0 (enable MP1) 2 1 1 1 1 1 0 (enableMP1) 3

In the evaluation phase, 5-input capacitive circuit 1000 can then behaveas an always on circuit that drives a constant logic value on node n1(when threshold is 0), an OR/NOR gate (when threshold is 1), amajority-0/minority-0 gate or a threshold gate (when threshold is 2), ora majority/minority gate (when threshold is 3). Note, this exampleassumes equal weights for C1, C2, C3, C4, and C5 (e.g., C1=C2=C3=C4=C5).In some embodiments, the threshold may change (e.g., from 1 to 2 or to3, 4, or 5 or any other value) when the ratio of capacitances ofcapacitors C1, C2, C3, C4, and/or C5 are modified.

FIG. 10B illustrates 5-input adjustable threshold gate 1020 with linearor paraelectric capacitors and a pull-down device on a summing node, inaccordance with some embodiments. Compared to FIG. 10A, here pull-updevice MP1 is removed and pull-down device MN1 is coupled to node n1 andground power supply rail. In various embodiments, during the resetphase, node n1 is pulled-down by MN1 to ground, and inputs ‘a’, ‘b’,‘c’, ‘d’ and ‘e’ are conditioned via configuration circuit 1022 toadjust the threshold of 5-input capacitive circuit 1000. Conditioningcircuitry 1022 may receive inputs in1, in2, in3, in4, and in5 andconfiguration setting (e.g., reset or evaluation) to determine theoutputs ‘a’, ‘b’, ‘c’, ‘d’, ‘e’, and control “down”. During theevaluation phase, in1 is passed on to output ‘a’, in2 is passed on to‘b’, in3 is passed on to ‘c’, in4 is passed on to ‘d’, and in5 is passedon to ‘e’. During the reset phase, depending on a desired threshold,outputs ‘a’, ‘b’, ‘c’ ‘d’, and ‘e’ are conditioned. Table 11 illustratesthat when inputs ‘a’, ‘b’, ‘c’, ‘d’, and ‘e’ are conditioned andpull-down device MN1 is enabled during the reset phase, then thethreshold is set to 3, 4, or 5. In this example, the capacitors compriselinear dielectric material.

TABLE 11 ‘a’ ‘b’ ‘c’ ‘d’ ‘e’ Second control (down) Threshold 0 0 0 0 0 1(enable MN1) 3 1 0 0 0 0 1 (enable MN1) 4 1 1 0 0 0 1 (enable MN1) 5 1 11 0 0 1 (enable MN1) 5 1 1 1 1 0 1 (enable MN1) 5 1 1 1 1 1 1 (enableMN1) 5

In the evaluation phase, 5-input capacitive circuit 1020 can then behaveas a majority/minority gate (when threshold is 3) or a threshold gate(when threshold is 4), or an AND/NAND gate (when threshold is 5). Note,this example assumes equal weights for C1, C2, C3, C4, and C5 (e.g.,C1=C2=C3=C4=C5). In some embodiments, the threshold may change (e.g.,from 3 to 2 or to 1, 4, or 5 or any other value) when the ratio ofcapacitances of capacitors C1, C2, C3, C4 and/or C5 are modified.

While the various embodiments illustrate the first input ‘a’, secondinput ‘b’, third input ‘c’, fourth input ‘d’, and/or fifth input ‘e’,these inputs are labeled for reference purposes and can be swapped inany order assuming all capacitors have the same capacitance. Inputassociated with capacitors of the same capacitance can be swapped withone another, in accordance with some embodiments. While the embodimentsare illustrated for capacitive input circuits with up to 5 inputs, theadaptive or configurable threshold for the capacitive circuit can beachieved for any number of inputs (e.g., n number of inputs) using thescheme discussed herein.

Table 12 illustrates that when inputs ‘a’, ‘b’, ‘c’, ‘d’, and ‘e’ areconditioned and pull-down device MN1 is enabled during the reset phase,then the threshold is set to 3, 4, 5, or 6. When the capacitors compriseparaelectric material, different thresholds are achieved compared to thelinear dielectric material for the same input conditioning. Table 12 isthe case when capacitors comprise paraelectric material.

TABLE 12 ‘a’ ‘b’ ‘c’ ‘d’ ‘e’ Second control (down) Threshold 0 0 0 0 0 1(enable MN1) 3 1 0 0 0 0 1 (enable MN1) 4 1 1 0 0 0 1 (enable MN1) 4 1 11 0 0 1 (enable MN1) 5 1 1 1 1 0 1 (enable MN1) 5 1 1 1 1 1 1 (enableMN1) 6

In the evaluation phase, 5-input capacitive circuit 1020 can then behaveas a majority/minority gate (when threshold is 3), a threshold gate(when threshold is 4), an AND/NAND gate (when threshold is 5), or adisconnected circuit (when threshold is 6). Note, this example assumesequal weights for C1, C2, C3, C4, and C5 (e.g., C1=C2=C3=C4=C5). In someembodiments, the threshold may change (e.g., from 3 to 2 or to 1, 4, or5 or any other value) when the ratio of capacitances of capacitors C1,C2, C3, C4 and/or C5 are modified.

FIG. 11 illustrates 2-input adjustable threshold gate 1100 withferroelectric capacitors and a pull-down device and a pull-up device ona summing node, in accordance with some embodiments. In someembodiments, 2-input capacitive circuit 1100 comprises a first input(a), a second input (b), summing node (n1), first capacitor C1, secondcapacitor C2, pull-up-device MP1, pull-down device MN1, driver 801, andoutput (out) coupled as shown. In some embodiments, the first capacitorC1 includes a first terminal coupled to the first input and a secondterminal coupled to the summing node n1. In some embodiments, the secondcapacitor C2 includes a third terminal coupled to the second input and afourth terminal coupled to the summing node n1. In some embodiments, thepull-up device MP1 is coupled to the summing node n1 and a power supplyrail Vdd, wherein the pull-up device MP1 is controlled by a firstcontrol (up). In some embodiments, the pull-down device MN1 is coupledto the summing node n1 and a ground, wherein the pull-down device iscontrolled by a second control (down).

In some embodiments, conditioning circuitry 1102 is provided which isused to control or condition the first input, the second input, thefirst control, and the second control during a reset phase to adjust athreshold of 2-input capacitive circuit 1100. Conditioning circuitry1102 may receive inputs in1 and in2, and configuration setting (e.g.,reset or evaluation) to determine the outputs ‘a’, ‘b’, up, and down.During the evaluation phase, in1 is passed on to output ‘a’ and in2 ispassed on to ‘b’. During the reset phase, depending on a desiredthreshold, outputs ‘a’ and ‘b’ are conditioned. In various embodiments,the pull-up device MP1 and pull-down device MN1 are turn on in asequence during reset phase while inputs to the capacitors are keptconstant for a particular threshold setting. In some embodiments, fordifferent input values, the threshold can be configured differently. Thesequence of turning on the pull-up device MP1 first and then thepull-down device MN1 can be reversed to readjust the threshold of thecircuit. In various embodiments, the pull-up device MP1 and pull-downdevice MN1 are turned off after the reset phase is complete.

Here the term threshold generally refers to a number that indicates anumber of inputs that should be set to logic high to perform a functionof a threshold gate. For instance, by turning on/off one or more of thepull-up device MP1 and/or pull-down device MN1, and conditioning theinputs ‘a’ and ‘b’ during a reset phase, the charge at node n1 is set sothat in an evaluation phase when the pull-up and pull-down devices (MP1and MN1) are disabled, the input capacitive circuit attains a desiredfunction.

In one instance, when the threshold is set to 2 in a reset phase by aparticular sequencing of turning on/off the pull-up and/or the pull-downdevices and conditioning of the inputs ‘a’ and ‘b; it means that duringan evaluation phase when both inputs ‘a’ and ‘b’ are logic high, thenvoltage on node n1 is logic high. Continuing with this example, when anyof the inputs ‘a’ and ‘b’ is a logic low, then the voltage on node n1resolves to logic low. As such, 2-input capacitive circuit 1100 isprogrammed or configured as a AND gate at node n1 and a NAND gate atoutput out.

Likewise, when the threshold is set to 1 in a reset phase by aparticular sequencing of turning on/off the pull-up and the pull-downdevices and conditioning of the inputs ‘a’ and ‘b; it means that duringan evaluation phase when either input ‘a’ and ‘b’ is logic high, thenvoltage on node n1 is logic high. Continuing with this example, whenboth the inputs ‘a’ and ‘b’ is a logic low, then the voltage on node n1resolves to logic low. As such, 2-input capacitive circuit 1100 isprogrammed or configured as an OR gate at node n1 and a NOR gate atoutput out. So, the same circuit can be used as an AND/NAND or OR/NORgate by conditioning the inputs and resetting or setting the voltage onthe summing node during a reset phase. Subsequently, in the evaluationphase the circuit will behave as AND/NAND or OR/NOR gate.

In some embodiments, conditioning circuitry 1102 turns off the pull-updevice MP1 and the pull-down device MN1 during an evaluation phaseseparate from the reset phase. The reset phase or evaluation phase areindicated by the logic level of Config. For example, conditioningcircuitry 1102 sets the first control (up) to logic high (Vdd) and thesecond control (down) to logic low (ground) during an evaluation phase(e.g., Config is set to logic 1). Likewise, in a reset phase, Config isset to 0. This is just an example, and the logic level of Config can bemodified to present the evaluation phase and the reset phase.

In some embodiments, conditioning circuitry 1102 sets the threshold to 0in a reset phase by first enabling or turning on the pull-down deviceMN1, and then turning on or enabling the pull-up device MP1, andproviding logic 0 to the first input and the second input. A thresholdof 0 means that the capacitive input circuit is an always on circuitregardless of the logic levels of inputs. In one such embodiment, duringthe evaluation phase for the circuit configured with threshold of zero,the logic value on node n1 is logic 1, and the logic value on output outis logic 0 (assuming the driver is an inverter).

In some embodiments, conditioning circuitry 1102 sets the threshold to 1in a reset phase by first enabling or turning on the pull-down deviceMN1, and then turning on the pull-up device MP1, and providing logic 1to the first input ‘a’ and logic 0 to the second input ‘b’. In someembodiments, conditioning circuitry 1102 sets the threshold to 1 in areset phase by first enabling or turning on the pull-up device MP1, andthen turning on or enabling the pull-down device MN1, and providinglogic 0 to the first input ‘a’ and to the second input ‘b’.

In some embodiments, conditioning circuitry 1102 sets the threshold to 2in a reset phase by first enabling or turning on the pull-up device MP1,and then turning on the pull-down device MN1, and providing logic 1 tothe first input ‘a’ and logic 0 the second input ‘b’. In someembodiments, conditioning circuitry 1102 sets the threshold to 2 in areset phase by first enabling or turning on the pull-down device MN1,and then turning on the pull-up device MP1, and providing logic 1 (e.g.,Vdd) to the first input ‘a’ and to the second input ‘b’.

In some embodiments, conditioning circuitry 1102 sets the threshold to 3in a reset phase by first enabling or turning on the pull-up device MP1,and then turning on or enabling the pull-down device MN1, and providinglogic 1 to the first input and the second input. A threshold of 3 for a2-input capacitive circuit means that capacitive input circuit is analways off circuit regardless of the logic levels of inputs. In one suchembodiment, during the evaluation phase for the circuit configured withthreshold of n+1 (e.g., 3, where ‘n’ is the number of capacitiveinputs), the logic value on node n1 is floating or drifting and thecharge on that node may eventually discharge to ground. In some cases,the voltage on node n1 may charge to supply level via the pull-up devicewhen the node n1 is floating. For example, initially the voltage on thefloating node discharges to zero voltages, but then it may charge up vialeakage to the supply voltage over time. In some embodiments, when thethreshold is n+1, the capacitive input circuit may not turn on even whenthe inputs to the capacitors are changing. In some embodiments, thevoltage on node n1 is zero volts regarding of input setting when thethreshold in n+1.

In some embodiments, a logic decides about the kind of logic function toconfigure 2-input capacitive circuit 1100. For example, a control logicblock or a conditioning circuit 1102 may determine whether 2-inputcapacitive circuit 1100 is to behave as an AND/NAND gate, an OR/NORgate, an always-on circuit, or a disconnected circuit.

In some embodiments, control logic block or a conditioning circuit 1102places 2-input capacitive circuit 1100 in a reset phase. In the resetphase, the inputs ‘a’ and ‘b’ and controls for the pull-up device MP1and pull-down device MN1 are set or conditioned to configure or adjustthe threshold for the 2-input capacitive circuit. In some embodiments,control logic block or conditioning circuit 1102 may adjust a thresholdof 2-input capacitive circuit 1100 to configure the 2-input capacitivecircuit 1100 as a particular logic function. When the input capacitorsare ferroelectric capacitors (because they include ferroelectricmaterial for their dielectric), control logic block or conditioningcircuit 1102 sequencies the turning on of the pull-up device MP1 and thepull-down device MN1 to achieve a particular threshold for a given setof inputs to the capacitors. In some embodiments, the pull-up device MP1is turned on before the pull-down device MN1. In some embodiments, thepull-down device MN1 is turned on before the pull-up device MP1.

Table 13 illustrates an example of input conditioning to set variousthresholds during a reset phase for 2-input capacitive circuit 1100. Invarious embodiments, during the sequence one of pull-up or pull-downdevice is on at a time to avoid crossbar current or short circuitcurrent. For example, when the pull-down device MN1 is enabled, thepull-up device MP1 is disabled. Likewise, when the pull-up device MP1 isenabled, the pull-down device MN1 is disabled. Here, time T3 (or eventT3) occurs after time T2 (or event T2) which occurs after time T1 (orevent T1). In some embodiments, the separation between T1, T2, and T3 isbetween ½ cycle to 1 cycle, where a cycle is in GHz (e.g., 1 GHz ormore).

TABLE 13 In- In- put put Thresh- ‘a’ ‘b’ Time T1 Time T2 Time T3 old 0 01 (enable MN1) 0 (disable MN1) 0 (enable MP1) 0 1 0 1 (enable MN1) 0(disable MN1) 0 (enable MP1) 1 1 1 1 (enable MN1) 0 (disable MN1)) 0(enable MP1) 2 0 0 0 (enable MP1) 1 (disable MP1) 1 (enable MN1) 1 1 0 0(enable MP1) 1 (disable MP1) 1 (enable MN1) 2 1 1 0 (enable MP1) 1(disable MP1) 1 (enable MN1) 3

While the embodiments are illustrated with reference to samecapacitances for first capacitor C1 and the second capacitor C2, thethreshold can be affected by changing the capacitive ratio of C1 and C2.For example, the input conditioning scheme and the pull-up and pull-downdevice control can result in a different threshold than that in Table 13when the capacitive ratio of C1 and C2 is not 1:1. Overall, theconfiguring scheme of various embodiments herein provide the flexibilityof programming the threshold for 2-input capacitive circuit 1100 in areset phase to achieve a certain logic function in the evaluation phase.

In some embodiments, control logic block or a conditioning circuit 1102releases the reset phase and allows the 2-input capacitive circuit toevaluate the inputs in the evaluation phase. Table 14 illustrates alogic function achieved in the evaluation phase by configuring oradjusting the threshold in the reset phase for 2-input capacitivecircuit 1100. In various embodiments, the pull-up device MP1 and thepull-down device MN1 are disabled during the evaluation phase.

TABLE 14 Logic Function Logic function on Threshold on node n1 node“out” 3 Logic 0 Logic 1 2 AND NAND 1 OR NOR 0 Logic 1 Logic 0

FIG. 12 illustrates 3-input adjustable threshold gate 1200 withferroelectric capacitors and a pull-down device and a pull-up device ona summing node, in accordance with some embodiments. 3-input capacitivecircuit 1200 is like 2-input capacitive circuit 1100 but for additionalinput ‘c’ and associated capacitor C3. In some embodiments, a firstterminal of capacitor C3 is coupled to input ‘c’ while a second terminalof capacitor C3 is coupled to summing node n1. Conditioning circuit 1102is replaced with a conditioning circuit 1202. Conditioning circuitry1202 may receive inputs in1, in2, and in3 and configuration setting(e.g., reset or evaluation) to determine the outputs ‘a’, ‘b’, ‘c’,controls “up”, and “down”. During the evaluation phase, in1 is passed onto output ‘a’, in2 is passed on to ‘b’, and in3 is passed on to ‘c’.During the reset phase, depending on a desired threshold, outputs ‘a’,‘b’, and ‘c’ are conditioned.

In some embodiments, by turning on/off the pull-up device MP1 andpull-down device MN1 in a sequence, and conditioning the inputs ‘a’,‘b’, and ‘c’ during a reset phase, the charge at node n1 is set. Assuch, in an evaluation phase when the pull-up and the pull-down devices(MP1 and MN1) are disabled, 3-input capacitive circuit 300 attains adesired function.

In some embodiments, conditioning circuitry 1202 sets the threshold to 0in a reset phase by first enabling or turning on the pull-down deviceMN1, and then turning on or enabling the pull-up device MP1, andproviding logic 0 to the first input ‘a’, logic 0 to the second input‘b’, and logic 0 to the third input ‘c’. A threshold of 0 means that thecapacitive input circuit is an always on circuit regardless of the logiclevels of inputs. In one such embodiment, during the evaluation phasefor the circuit configured with threshold of zero, the logic value onnode n1 is logic 1, and the logic value on output out is logic 0(assuming the driver is an inverter).

In some embodiments, conditioning circuitry 1202 sets the threshold to 1in a reset phase by first enabling or turning on the pull-down deviceMN1, and then turning on or enabling the pull-up device MP1, andproviding logic 1 to the first input ‘a’, logic 0 to the second input‘b’, and logic 0 to the third input ‘c’. In some embodiments,conditioning circuitry 1202 sets the threshold to 1 in a reset phase byfirst enabling or turning on the pull-up device MP1, and then turning onor enabling the pull-down device MN1, and providing logic 0 to the firstinput ‘a’, logic 0 to the second input ‘b’, and logic 0 to the thirdinput ‘c’. In some embodiments, when the threshold is set to 1 in areset phase by a particular sequencing of turning on/off the pull-up andthe pull-down devices and conditioning of the inputs ‘a’, ‘b’, and ‘c’;it means that during an evaluation phase when any of the inputs ‘a’ ‘b’,or ‘c’ is logic high, then voltage on node n1 is logic high. Continuingwith this example, in the evaluation phase when all inputs ‘a’, ‘b’, or‘c’ are a logic low, then the voltage on node n1 resolves to logic low.As such, 3-input capacitive circuit 1200 is programmed or configured asan OR gate at node n1 and a NOR gate at output out (assuming the drivercircuitry is an inverter).

In some embodiments, conditioning circuitry 1202 sets the threshold to 2in a reset phase by first enabling or turning on the pull-down deviceMN1, and then turning on or enabling the pull-up device MP1, andproviding logic 1 to the first input ‘a’, logic 1 to the second input‘b’, and logic 0 to the third input ‘c’. In some embodiments,conditioning circuitry 1202 sets the threshold to 2 in a reset phase byfirst enabling or turning on the pull-up device MP1, and then turning onor enabling the pull-down device MN1, and providing logic 1 to the firstinput ‘a’, logic 0 to the second input ‘b’, and logic 0 to the thirdinput ‘c’. In some embodiments, when the threshold is set to 2 in areset phase by a particular sequencing of turning on/off the pull-up andthe pull-down devices and conditioning of the inputs ‘a’, ‘b’, and ‘c’;it means that during an evaluation phase when at least two of the threeinputs ‘a’, ‘b’, and ‘c’ are logic high, then voltage on node n1 islogic high. Continuing with this example, when at least two inputs ofthe three inputs ‘a’ ‘b’, and ‘c’ is a logic low, then the voltage onnode n1 resolves to logic low. As such, 3-input capacitive circuit 1200is programmed or configured as a majority gate at node n1 and a minoritygate at output out (when the driver circuitry is an inverter). In somecases, depending upon the leakage balance of pull-up transistor MP1 andpull-down MN1 as it impacts charge on the summing node n1, 3-inputcapacitive circuit 1200 may lose its majority logic functionality overtime. This loss in functionality of the majority function can berestored by resetting the summing node n1 via transistors MP1 and MN1,in accordance with some embodiments.

In some embodiments, conditioning circuitry 1202 sets the threshold to 3in a reset phase by first enabling or turning on the pull-down deviceMN1, and then turning on or enabling the pull-up device MP1, andproviding logic 1 to the first input ‘a’, logic 1 to the second input‘b’, and logic 1 to the third input ‘c’. In some embodiments,conditioning circuitry 1202 sets the threshold to 3 in a reset phase byfirst enabling or turning on the pull-up device MP1, and then turning onor enabling the pull-down device MN1, and providing logic 1 to the firstinput ‘a’, logic 1 to the second input ‘b’, and logic 0 to the thirdinput ‘c’. In some embodiments, when the threshold is set to 3 in areset phase by a particular sequencing of turning on/off the pull-up andthe pull-down devices and conditioning of the inputs ‘a’, ‘b’, and ‘c’;it means that during an evaluation phase when all three inputs ‘a’, ‘b’,and ‘c’ are logic high, then voltage on node n1 is logic high.Continuing with this example, when any of the three inputs ‘a’ ‘b’, and‘c’ is a logic low, then the voltage on node n1 resolves to logic low.As such, 3-input capacitive circuit 1200 is programmed or configured asa 3-input AND at node n1 and a 3-input NAND gate at output out (assumingthe driver circuitry is an inverter).

In some embodiments, conditioning circuitry 1202 sets the threshold to 4in a reset phase by first enabling or turning on the pull-up device MP1,and then turning on or enabling the pull-down device MN1, and providinglogic 1 to the first input ‘a’, the second input ‘b’, and the thirdinput ‘c’. A threshold of 4 for a 3-input capacitive circuit means thatcapacitive input circuit is an always off circuit regardless of thelogic levels of the inputs. In one such embodiment, during theevaluation phase for the circuit configured with threshold of n+1 (e.g.,4, where ‘n’ is the number of capacitive inputs), the logic value onnode n1 is floating and may eventually discharge to ground or charge tosupply level. In some embodiments, the voltage on node n1 is zero voltsregarding of input setting when the threshold in 4 (e.g., n+1).

So, the same circuit can be used as a majority/minority gate, AND/NAND,OR/NOR, always-on gate, or a disconnected gate by conditioning theinputs and resetting or setting the voltage on the summing node during areset phase. Subsequently, in the evaluation phase the circuit willbehave as a 3-input majority/minority, a 3-input AND/NAND, a 3-inputOR/NOR gate, a 3-input always-on gate, or a 3-input disconnected gate.

In some embodiments, a logic decides about the kind of logic function toconfigure 3-input capacitive circuit 1200. For example, a control logicblock or a conditioning circuit 1202 may determine whether 3-inputcapacitive circuit 1200 is to behave as an always-on circuit, alwaysdisconnected circuit, a majority/minority, an AND/NAND gate, or anOR/NOR gate. In some embodiments, control logic block or conditioningcircuit 1202 may adjust a threshold of 3-input capacitive circuit 1200to configure the 3-input capacitive circuit 1200 as a particular logicfunction.

In some embodiments, control logic block or a conditioning circuit 1202places 3-input capacitive circuit 1200 in a reset phase. In the resetphase, the inputs ‘a’, ‘b’, and ‘c’ and controls for the pull-up deviceMP1 and pull-down device MN1 are set or conditioned to configure oradjust the threshold for the 3-input capacitive circuit. In someembodiments, control logic block or a conditioning circuit 1202 mayadjust a threshold of 3-input capacitive circuit 1200 to configure the3-input capacitive circuit 1200 as a particular logic function. When theinput capacitors are ferroelectric capacitors (because they includeferroelectric material for their dielectric), control logic block or aconditioning circuit 1202 sequences the turning on of the pull-up deviceMP1 and the pull-down device MN1 to achieve a particular threshold for agiven set of inputs to the capacitors. In some embodiments, the pull-updevice MP1 is turned on before the pull-down device MN1. In someembodiments, the pull-down device MN1 is turned on before the pull-updevice MP1.

Table 15 illustrates an example of input conditioning to set variousthresholds during a reset phase for 3-input capacitive circuit 1200. Invarious embodiments, during the sequence one of pull-up or pull-downdevice is on at a time to avoid crossbar current or short circuitcurrent. For example, when the pull-down device MN1 is enabled, thepull-up device MP1 is disabled. Likewise, when the pull-up device MP1 isenabled, the pull-down device MN1 is disabled. Here, time T3 (or eventT3) occurs after time T2 (or event T2) which occurs after time T1 (orevent T1). In some embodiments, the separation between T1, T2, and T3 isbetween ½ cycle to 1 cycle, where a cycle is in GHz (e.g., 1 GHz ormore).

TABLE 15 ‘a’ ‘b’ ‘c’ T1 T2 T3 Threshold 0 0 0 1 (enable MN1) 0 (disableMN1) 0 (enable MP1) 0 1 0 0 1 (enable MN1) 0 (disable MN1) 0 (enableMP1) 1 1 1 0 1 (enable MN1) 0 (disable MN1) 0 (enable MP1) 2 1 1 1 1(enable MN1) 0 (disable MN1) 0 (enable MP1) 3 0 0 0 0 (enable MP1) 1(disable MP1) 1 (enable MN1) 1 1 0 0 0 (enable MP1) 1 (disable MP1) 1(enable MN1) 2 1 1 0 0 (enable MP1) 1 (disable MP1) 1 (enable MN1) 3 1 11 0 (enable MP1) 1 (disable MP1) 1 (enable MN1) 4

While the embodiments are illustrated with reference to the samecapacitances for the first capacitor C1, the second capacitor C2, andthe third capacitor C3, the threshold can be affected by changing thecapacitive ratio of C1, C2, and C3 relative to one another. For example,the input conditioning scheme and the pull-up and pull-down devicecontrol can result in a different threshold than that in Table 15 whenthe capacitive ratio of C1, C2, and C3 is not 1:1:1. Overall, theconfiguring scheme of various embodiments herein provide the flexibilityof programming or adjusting the threshold for 3-input capacitive circuit1200 in a reset phase to achieve a certain logic function in theevaluation phase.

In some embodiments, control logic block or a conditioning circuit 1202releases the reset phase and allows 3-input capacitive circuit toevaluate the inputs in the evaluation phase. Table 16 illustrates alogic function achieved in the evaluation phase by configuring thethreshold in the reset phase for 3-input capacitive circuit 1200. Invarious embodiments, the pull-up device MP1 and the pull-down device MN1are disabled during the evaluation phase.

TABLE 16 Logic Function Logic function on Threshold on node n1 node“out” 0 Logic 1 Logic 0 1 OR NOR 2 Majority Minority 3 AND NAND 4 Logic0 Logic 1

FIG. 13 illustrates 5-input adjustable threshold gate 1300 withferroelectric capacitors and a pull-down device and a pull-up device ona summing node, in accordance with some embodiments. 5-input capacitivecircuit 1300 is like 3-input capacitive circuit 1100 but for additionalinputs ‘d’ and ‘e’ and associated capacitors C4 and C5. In someembodiments, a first terminal of capacitor C4 is coupled to input ‘d’while a second terminal of capacitor C4 is coupled to summing node n1.In some embodiments, a first terminal of capacitor C5 is coupled toinput ‘e’ while a second terminal of capacitor C5 is coupled to summingnode n1. Conditioning circuit 1202 is replaced with a conditioningcircuit 1302. Conditioning circuitry 1302 may receive inputs in1, in2,in3, in4, and in5 and configuration setting (e.g., reset or evaluation)to determine the outputs ‘a’, ‘b’, ‘c’, ‘d’, ‘e’, controls “up”, and“down”. During the evaluation phase, in1 is passed on to output ‘a’, in2is passed on to ‘b’, in3 is passed on to ‘c’, in4 is passed on to ‘d’,and in5 is passed on to ‘e’. During the reset phase, depending on adesired threshold, outputs ‘a’, ‘b’, ‘c’ ‘d’, and ‘e’ are conditioned.

In some embodiments, by turning on/off the pull-up device MP1 andpull-down device MN1 in a sequence, and conditioning the inputs ‘a’,‘b’, ‘c’, ‘d’, and ‘e’ during a reset phase, the charge at node n1 isset. As such, in an evaluation phase when the pull-up and pull-downdevices (MP1 and MN1) are disabled, 5-input capacitive circuit 500attains a desired function.

In some embodiments, conditioning circuitry 1302 sets the threshold to 0in a reset phase by first enabling or turning on the pull-down deviceMN1, and then turning on or enabling the pull-up device MP1, andproviding logic 0 to the first input ‘a’, logic 0 to the second input‘b’, and logic 0 to the third input ‘c’, logic 0 to the fourth input‘d’, and logic 0 to the fifth input ‘e’. A threshold of 0 means thatconditioning circuitry 1302 is an always on circuit regardless of thelogic levels of inputs. In one such embodiment, during the evaluationphase for the circuit configured with threshold of zero, the logic valueon node n1 is logic 1, and the logic value on output out is logic 0(assuming the driver is an inverter).

In some embodiments, conditioning circuitry 1302 sets the threshold to 1in a reset phase by first enabling or turning on the pull-down deviceMN1, and then turning on or enabling the pull-up device MP1, andproviding logic 1 to the first input ‘a’, logic 0 to the second input‘b’, and logic 0 to the third input ‘c’, logic 0 to the fourth input‘d’, and logic 0 to the fifth input ‘e’. In some embodiments,conditioning circuitry 1302 sets the threshold to 1 in a reset phase byfirst enabling or turning on the pull-up device MP1, and then turning onor enabling the pull-down device MN1, and providing logic 0 to the firstinput ‘a’, logic 0 to the second input ‘b’, and logic 0 to the thirdinput ‘c’, logic 0 to the fourth input ‘d’, and logic 0 to the fifthinput ‘e’. In some embodiments, when the threshold is set to 1 in areset phase by a particular sequencing of turning on/off the pull-up andthe pull-down devices and conditioning of the inputs ‘a’ ‘b’, ‘c’, ‘d’,and ‘e’; it means that during an evaluation phase when any of the inputs‘a’ ‘b’, ‘c’, ‘d’, or ‘e’ is logic high, then voltage on node n1 islogic high. Continuing with this example, when all inputs ‘a’, ‘b’, ‘c’‘d’, or ‘e’ is a logic low, then the voltage on node n1 resolves tologic low. As such, 5-input capacitive circuit 1300 is programmed orconfigured as an OR gate at node n1 and an NOR gate at output out.

In some embodiments, conditioning circuitry 1302 sets the threshold to 2in a reset phase by first enabling or turning on the pull-down deviceMN1, and then turning on or enabling the pull-up device MP1, andproviding logic 1 to the first input ‘a’, logic 1 to the second input‘b’, and logic 0 to the third input ‘c’, logic 0 to the fourth input‘d’, and logic 0 to the fifth input ‘e’. In some embodiments,conditioning circuitry 1302 sets the threshold to 2 in a reset phase byfirst enabling or turning on the pull-up device MP1, and then turning onor enabling the pull-down device MN1, and providing logic 1 to the firstinput ‘a’, logic 0 to the second input ‘b’, and logic 0 to the thirdinput ‘c’, logic 0 to the fourth input ‘d’, and logic 0 to the fifthinput ‘e’. In one instance, when the threshold is set to 2 in a resetphase by a particular sequencing of turning on/off the pull-up and thepull-down devices and conditioning of the inputs ‘a’, ‘b’, ‘c’, ‘d’, and‘e’; it means that during an evaluation phase when at least two of thefive inputs ‘a’, ‘b’ ‘c’, ‘d’, and ‘e’ are logic high, then voltage onnode n1 is logic high. Continuing with this example, when one or zeroinputs of the five inputs ‘a’ ‘b’, ‘c’, ‘d’, and ‘e’ are a logic high,then the voltage on node n1 resolves to logic low. As such, 5-inputcapacitive circuit 1300 is programmed or configured as a 5-inputmajority 0 gate-like logic (e.g., a threshold gate with a threshold of2) at node n1 and a 5-input minority 0 gate-like logic (e.g., aninverted threshold gate with a threshold of 2) at output out.

In some embodiments, conditioning circuitry 1302 sets the threshold to 3in a reset phase by first enabling or turning on the pull-down deviceMN1, and then turning on or enabling the pull-up device MP1, andproviding logic 1 to the first input ‘a’, logic 1 to the second input‘b’, and logic 1 to the third input ‘c’, logic 0 to the fourth input‘d’, and logic 0 to the fifth input ‘e’. In some embodiments,conditioning circuitry 1302 sets the threshold to 3 in a reset phase byfirst enabling or turning on the pull-up device MP1, and then turning onor enabling the pull-down device MN1, and providing logic 1 to the firstinput ‘a’, logic 1 to the second input ‘b’, and logic 0 to the thirdinput ‘c’, logic 0 to the fourth input ‘d’, and logic 0 to the fifthinput ‘e’. In one instance, when the threshold is set to 3 in a resetphase by a particular sequencing of turning on/off the pull-up and/orthe pull-down devices and conditioning of the inputs ‘a’, ‘b’, ‘c’, ‘d’,and ‘e’; it means that during an evaluation phase when at least three ofthe five inputs ‘a’, ‘b’ ‘c’, ‘d’, and ‘e’ are logic high, then voltageon node n1 is logic high. Continuing with this example, when at leasttwo inputs of the five inputs ‘a’ ‘b’, ‘c’, ‘d’, and ‘e’ is a logic low(or 2 or fewer inputs are logic high), then the voltage on node n1resolves to logic low. As such, 5-input capacitive circuit 1300 isprogrammed or configured as a 5-input majority gate logic at node n1 anda 5-input minority gate logic at output out (assuming driver circuitry801 is an inverter).

In some embodiments, conditioning circuitry 1302 sets the threshold to 4in a reset phase by first enabling or turning on the pull-down deviceMN1, and then turning on or enabling the pull-up device MP1, andproviding logic 1 to the first input ‘a’, logic 1 to the second input‘b’, and logic 1 to the third input ‘c’, logic 1 to the fourth input‘d’, and logic 0 to the fifth input ‘e’. In some embodiments,conditioning circuitry 1302 sets the threshold to 4 in a reset phase byfirst enabling or turning on the pull-up device MP1, and then turning onor enabling the pull-down device MN1, and providing logic 1 to the firstinput ‘a’, logic 1 to the second input ‘b’, and logic 1 to the thirdinput ‘c’, logic 0 to the fourth input ‘d’, and logic 0 to the fifthinput ‘e’. In some embodiments, when the threshold is set to 4 in areset phase by a particular sequencing of turning on/off the pull-up andthe pull-down devices and conditioning of the inputs ‘a’, ‘b’, ‘c’, ‘d’,and ‘e’; it means that during an evaluation phase when at least fourinputs from the five inputs ‘a’, ‘b’ ‘c’, ‘d’ and ‘e’ are logic high,then voltage on node n1 is logic high. Continuing with this example,when three or fewer inputs from the five inputs ‘a’ ‘b’, ‘c’, ‘d’ and‘e’ are logic high, then the voltage on node n1 resolves to logic low.As such, 5-input capacitive circuit 1300 is programmed or configured asa 5-input majority 1 gate-like logic (e.g., a threshold gate with athreshold of 4) at node n1 and a 5-input minority 1 gate-like logic(e.g., an inverted threshold gate with a threshold of 4) at output out.

In some embodiments, conditioning circuitry 1302 sets the threshold to 5in a reset phase by first enabling or turning on the pull-down deviceMN1, and then turning on or enabling the pull-up device MP1, andproviding logic 1 to the first input ‘a’, logic 1 to the second input‘b’, and logic 1 to the third input ‘c’, logic 1 to the fourth input‘d’, and logic 1 to the fifth input ‘e’. In some embodiments,conditioning circuitry 1302 sets the threshold to 5 in a reset phase byfirst enabling or turning on the pull-up device MP1, and then turning onor enabling the pull-down device MN1, and providing logic 1 to the firstinput ‘a’, logic 1 to the second input ‘b’, and logic 1 to the thirdinput ‘c’, logic 1 to the fourth input ‘d’, and logic 0 to the fifthinput ‘e’. In some embodiments, when the threshold is set to 5 in areset phase by a particular sequencing of turning on/off the pull-up andthe pull-down devices and conditioning of the inputs ‘a’, ‘b’, ‘c’, ‘d’,and ‘e’; it means that during an evaluation phase when all five inputs‘a’, ‘b’ ‘c’, ‘d’, and ‘e’ are logic high, then voltage on node n1 islogic high. Continuing with this example, when any of the five inputs‘a’ ‘b’, ‘c’, ‘d’, and ‘e’ is a logic low, then the voltage on node n1resolves to logic low. As such, 5-input capacitive circuit 1300 isprogrammed or configured as a 5-input AND at node n1 and a 5-input NANDgate at output out (assuming that the driver circuitry 801 is aninverter).

In some embodiments, conditioning circuitry 1302 sets the threshold to 6in a reset phase by first enabling or turning on the pull-up device MP1,and then turning on or enabling the pull-down device MN1, and providinglogic 1 to the first input ‘a’, logic 1 to the second input ‘b’, andlogic 1 to the third input ‘c’, logic 1 to the fourth input ‘d’, andlogic 1 to the fifth input ‘e’. A threshold of 6 for a 5-inputcapacitive circuit means that capacitive input circuit is an always offcircuit regardless of the logic levels of the inputs. In one suchembodiment, during the evaluation phase for the circuit configured withthreshold of n+1 (e.g., 6, where ‘n’ is the number of capacitiveinputs), the logic value on node n1 is floating and may eventuallydischarge to ground or charge to supply level. In some embodiments, thevoltage on node n1 is zero volts regarding of input setting when thethreshold in 6 (e.g., n+1).

So, the same circuit can be used as a majority/minority gate logicmajority/minority gate-like logic (or threshold logic gate), AND/NAND,OR/NOR gate, a gate driving a predetermined output, or a disconnectedgate by conditioning the inputs and resetting or setting the voltage onthe summing node in a sequence during a reset phase. Subsequently, inthe evaluation phase the circuit will behave as a 5-inputmajority/minority gate logic, 5-input majority/minority gate-like orthreshold logic, 5-input AND/NAND gate, 5-input OR/NOR gate, analways-on gate, or a disconnected gate.

Table 17 illustrates an example of input conditioning to set variousthresholds during a reset phase for 5-input capacitive circuit 1300. Invarious embodiments, during the sequence one of pull-up or pull-downdevice is on at a time to avoid crossbar current or short circuitcurrent. For example, when the pull-down device MN1 is enabled, thepull-up device MP1 is disabled. Likewise, when the pull-up device MP1 isenabled, the pull-down device MN1 is disabled. Here, time T3 (or eventT3) occurs after time T2 (or event T2) which occurs after time T1 (orevent T1). In some embodiments, the separation between T1, T2, and T3 isbetween ½ cycle to 1 cycle, where a cycle is in GHz (e.g., 1 GHz ormore).

TABLE 17 a b c d e T1 T2 T3 Threshold 0 0 0 0 0 1 (enable MN1) 0(disable MN1) 0 (enable MP1) 0 1 0 0 0 0 1 (enable MN1) 0 (disable MN1)0 (enable MP1) 1 1 1 0 0 0 1 (enable MN1) 0 (disable MN1) 0 (enable MP1)2 1 1 1 0 0 1 (enable MN1) 0 (disable MN1) 0 (enable MP1) 3 1 1 1 1 0 1(enable MN1) 0 (disable MN1) 0 (enable MP1) 4 1 1 1 1 1 1 (enable MN1) 0(disable MN1) 0 (enable MP1) 5 0 0 0 0 0 0 (enable MP1) 1 (disable MP1)1 (enable MN1) 1 1 0 0 0 0 0 (enable MP1) 1 (disable MP1) 1 (enable MN1)2 1 1 0 0 0 0 (enable MP1) 1 (disable MP1) 1 (enable MN1) 3 1 1 1 0 0 0(enable MP1) 1 (disable MP1) 1 (enable MN1) 4 1 1 1 1 0 0 (enable MP1) 1(disable MP1) 1 (enable MN1) 5 1 1 1 1 1 0 (enable MP1) 1 (disable MP1)1 (enable MN1) 6

Table 18 illustrates a logic function achieved in the evaluation phaseby configuring the threshold in the reset phase for 5-input capacitivecircuit 1300. In various embodiments, the pull-up device MP1 and thepull-down device MN1 are disabled during the evaluation phase.

TABLE 18 Threshold Logic Function on node n1 Logic function on node“out” 0 Logic 1 Logic 0 1 OR NOR 2 Majority 0 gate-like Minority 0gate-like (e.g., a threshold gate with (e.g., an inverted threshold athreshold of 2) gate with a threshold of 2) 3 Majority gate Minoritygate 4 Majority 1 gate-like Minority 1 gate-like (e.g., a threshold gatewith (e.g., an inverted threshold a threshold of 4) gate with athreshold of 4) 5 AND NAND 6 Logic 0 Logic 1

By setting inputs to have a particular number of 0 s and 1 s and at thesame time controlling the logic level appearing at the summation node(n1) by controlling the pull-up and pull-down devices in a sequence, twoeffects are accomplished, in accordance with various embodiments. First,each capacitor stores a deterministic charge. Second, a specificdisplacement charge is put on the summing or floating node n1. Setting aspecific displacement charge value at the floating node n1 sets thethreshold of when the floating node (n1) during the evaluation phase isallowed to go to the logic value of 0 or 1. For example, for an n-inputthreshold gate, if the threshold is set such that the floating node n1goes closer to 1 logic level than 0 logic level, when all of the inputsare set to 1, then the capacitive input circuit becomes a NAND gate.Similarly, if it is desired that any one input becomes logic 1 in theevaluation phase to give voltage closer to logic level 1 at the floatingnode, then the circuit becomes an OR gate with n-inputs. Similarly, anyintermediate threshold from 0 to n can be set. In some embodiments, athreshold of zero means that the gate becomes a buffer. For instance,the circuit is always turned on to input logic level 1. A threshold ofn+1 for an n-input gate means that the summation node n1 may not gocloser to logic level 1, even when all the inputs are set to 1. Thiswould mean that that the capacitive input circuit becomes a disconnectedcircuit.

In general, the input capacitive circuit when configured as a thresholdgate, it can be expressed as:

Y=1 if Σ_(j=1) ^(m) W _(j) X _(j) ≥T,

Y=0 if Σ_(j=1) ^(m) W _(j) X _(j) <T,

Where ‘Y’ is the output (logic level on node n1), ‘X’ is the input, ‘W’is the capacitive weight, and ‘T’ is the threshold. Assuming all Ws areones (e.g., all capacitors have the same capacitance), when T is equalto the number of inputs, and AND gate is realized at node n1. In thisexample, for a 3-input capacitive circuit, a 3 input AND gate isrealized when threshold is set to 3. In another example, when T equals1, a NOR gate is realized at node n1. In yet another example, when T isequal to 0, the input capacitive circuit is always on, and the voltageon node n1 is logic 1. In yet another example, when T is greater thanthe number of inputs to the circuit, the circuit is always off ordisconnected. In this case, voltage on node n1 is floating and may overtime leak away.

While the embodiments are described with reference to up-to 5-inputcapacitive circuit using equal ratio for the capacitance, the same ideacan be expanded to any number of input capacitive circuit with equal orunequal ratio for capacitances. In various embodiments, the capacitancesare ferroelectric capacitors. In some embodiments, the ferroelectriccapacitors are planar capacitors. In some embodiments, the ferroelectriccapacitors are pillar or trench capacitors. In some embodiments, theferroelectric capacitors are vertically stacked capacitors to reduce theoverall footprint of the multi-input capacitive circuit.

In some embodiments, the transistors (MP1 and MN1) that charge ordischarge the summing node n1 are planar or non-planar transistors. Insome embodiments, transistors MP1 and MN1 are fabricated in thefront-end of the die on a substrate. In some embodiments, one of thetransistors (e.g., MP1 or MN1) is fabricated in the front-end of the diewhile another one of the transistors is fabricated in the backend of theend such that the stack of capacitors is between the frontend of the dieand the backend of the die or between the two transistors. As such, thefootprint of the multi-input capacitive circuit may be a footprint of asingle transistor or slightly more than that. These backed transistorsor switches can be fabricated using any suitable technology such as IGZO(Indium gallium zinc oxide). In some embodiments, the ferroelectriccapacitors can be formed using transistors configured as capacitors,where transistor gates have ferroelectric material. These capacitors canbe on the frontend or the backend of the die.

While the various embodiments are described with reference to drivercircuitry 801 connected at node n1, driver circuitry 801 can be removed.When input capacitors for a capacitive input circuit are linearcapacitors (e.g., comprising linear dielectric material), the voltagedeveloped at node n1 may not reach rail-to-rail. As such, the subsequentdriver circuitry 801 connected to node n1 may experience static leakage.Static leakage increases power consumption. In various embodiments, wheninput capacitors comprise nonlinear polar material (e.g., ferroelectricmaterial), then the voltage developed on node n1 results in reducedstatic leakage in the subsequent driver circuitry 801. One reason forthis reduced leakage is because ferroelectric material in the inputcapacitors allow for voltage on node n1 to reach closer to rail-to-railvoltage, which reduces static leakage in subsequent driver circuitry801. Here, summation node n1 can maintain displacement charge (toprovide logic 0 or logic 1 functions for the programmed threshold) for alonger period compared to linear capacitors. Consequently, the resetoverhead of turning on/off the pull-up or pull-down devices is reduced.For example, when the leakage at the summation node n1 is low, thepull-up or pull-down devices may not need to turn on for tens ofmicroseconds, which reduces the reset activity on node n1. Thus, circuitusing nonlinear capacitors (e.g., ferroelectric capacitor) in thisconfiguration becomes a viable option to realize low leakage logiccircuits for advanced process technology nodes (e.g., advanced finFETprocess technology node).

Since the voltage on node n1 for the various threshold gates describedherein is closer to rail-to-rail voltage compared to the case whenlinear input capacitors are used, subsequent driver circuitry 801 can beremoved. As such, the input capacitors with nonlinear polar material candrive another capacitive input circuit directly. Here, closer torail-to-rail voltage on node n1 using nonlinear polar material basedcapacitors (e.g., ferroelectric or paraelectric capacitors) implies thatthe static leakage in the subsequent driver 801 is reduced compared tothe case when voltage on n1 is not close to rail-to-rail voltage. Whenlinear capacitors are used, a voltage divider is formed on node n1 basedon the number of capacitors and their logic inputs. Such a voltagedivider results in non-rail-to-rail voltage on node n1 that results instatic leakage in the subsequent driver 801. When nonlinear capacitorsare used, the voltage divider is not a linear voltage divider. Thisresults in a much closer rail-to-rail voltage on n1 which reduces staticleakage in the subsequent driver 801. Higher the nonlinearity, thecloser the voltage on node n1 is rail-to-rail. Nonlinear capacitors asshown in various embodiments allow the logic gate to have more inputscompared to the case when linear capacitors are used while keeping theleakage through diver 801 low.

FIG. 14 illustrates planar linear capacitor structure 1400, inaccordance with some embodiments. In some embodiments, capacitors forthe multi-input capacitive structures are linear capacitors. Thesecapacitors can take any planar form. One such form is illustrated inFIG. 14 . Here, planar capacitor structure 1400 is ametal-insulator-metal (MIM) capacitor comprising a bottom electrode, atop electrode, and a linear dielectric between the top electrode and thebottom electrode as shown. In some embodiments, conductive oxidelayer(s) are formed between the bottom electrode and the lineardielectric. In some embodiments, conductive oxide layer(s) are formedbetween the top electrode and the linear dielectric. Examples ofconductive oxides include: IrO₂, RuO₂, PdO₂, OsO₂, or ReO₃. In someexamples, conductive oxides are of the form A2O3 (e.g., In2O3, Fe2O3)and ABO3 type, where ‘A’ is a rare earth element and B is Mn.

In some embodiments, the dielectric layer includes one or more of: SiO2,Al2O3, Li2O, HfSiO4, Sc2O3, SrO, HfO2, ZrO2, Y2O3, Ta2O5, BaO, WO3,MoO3, or TiO2. Any suitable conductive material may be used for the topelectrode and the bottom electrode. For example, the material or theelectrode may include one or more of: Cu, Al, Ag, Au, W, or Co. In someembodiments, the thickness along the z-axis of the top electrode andbottom electrode is in a range of 1 nm to 30 nm. In some embodiments,the thickness along the z-axis of the dielectric is in a range of 1 nmto 30 nm. In some embodiments, the thickness along the z-axis of theconductive oxide is in a range of 1 nm to 30 nm.

FIG. 15A illustrates a non-planar linear capacitor structure 1500, inaccordance with some embodiments. In some embodiments, non-planarcapacitor structure 600 is rectangular in shape. Taking the cylindricalshaped case for example, in some embodiments, the layers of non-planarcapacitor structure 1500 from the center going outwards include bottomelectrode 1501 a, first conductive oxide 1512 a, linear dielectricmaterial 1513, second conductive oxide 1512 b, and top electrode 1501 b.A cross-sectional view along the “ab” dashed line is illustrated in themiddle of FIG. 15A. In some embodiments, conducting oxides are removedand the linear dielectric is directly connected to top electrode 1501 band bottom electrodes 1501 a. In some embodiments, linear dielectricmaterial 1513 can include any suitable dielectric, where the thicknessof dielectric film is a range of 1 nm to 20 nm. In some embodiments,linear dielectric material 1513 comprises a higher-K dielectricmaterial. In some embodiments, linear dielectrics include one of: SIO2,Al2O3, Li2O, HfSiO4, Sc2O3, SrO, HfO2, ZrO2, Y2O3, Ta2O5, BaO, WO3,MoO3, or TiO2. The high-k dielectric material may include elements suchas: zinc, niobium, scandium, lean yttrium, hafnium, silicon, strontium,oxygen, barium, titanium, zirconium, tantalum, aluminum, and lanthanum.Examples of high-k materials that may be used in the gate dielectriclayer include lead zinc niobate, hafnium oxide, lead scandium tantalumoxide, hafnium silicon oxide, yttrium oxide, aluminum oxide, lanthanumoxide, barium strontium titanium oxide, lanthanum aluminum oxide,titanium oxide, zirconium oxide, tantalum oxide, and zirconium siliconoxide.

In some embodiments, first conductive oxide 1512 a is conformallydeposited over bottom electrode 1501 a. In some embodiments, dielectricmaterial 1513 is conformally deposited over first conductive oxide 1512a. In some embodiments, second conductive oxide 1512 b is conformallydeposited over dielectric material 1513. In some embodiments, topelectrode 1501 b is conformally deposited over second conductive oxide1512 b. In some embodiments, bottom electrode 1501 a is in the centerwhile top electrode 1501 b is on an outer circumference of non-planarcapacitor structure 1500.

In some embodiments, material for bottom electrode 1501 a may includeone or more of: Cu, Al, Ag, Au, W, or Co, or their alloys. In someembodiments, material for first conductive oxide 1512 a include: IrO₂,RuO₂, PdO₂, OsO₂, or ReO₃. In some examples, conductive oxides are ofthe form A2O3 (e.g., In2O3, Fe2O3) and ABO3 type, where ‘A’ is a rareearth element and B is Mn. In some embodiments, material for secondconductive oxide 1512 b may be same as the material for first conductiveoxide 1512 a. In some embodiments, material for top electrode 1501 b mayinclude one or more of: Cu, Al, Ag, Au, W, or Co, or their alloys.

In some embodiments, a first refractive inter-metallic layer (not shown)is formed between dielectric material 1513 and first conductive oxide1512 a. In some embodiments, a second refractive inter-metallic layer(not shown) is formed between dielectric capacitor material 1513 andsecond conductive oxide 1512 b. In these cases, the first and secondrefractive inter-metallic layers are directly adjacent to theirrespective conductive oxide layers and to dielectric capacitor material1513. In some embodiments, refractive inter-metallic maintains thecapacitive properties of the dielectric capacitor material 1513. In someembodiments, refractive inter-metallic comprises Ti and Al (e.g., TiAlcompound). In some embodiments, refractive inter-metallic comprises oneor more of Ta, W, and/or Co.

For example, refractive inter-metallic includes a lattice of Ta, W, andCo. In some embodiments, refractive inter-metallic includes one of:Ti—Al such as Ti3Al, TiAl, TiAl3; Ni—Al such as Ni3Al, NiAl3, NiAl;Ni—Ti, Ni—Ga, Ni2MnGa; FeGa, Fe3Ga; borides, carbides, or nitrides. Insome embodiments, TiAl material comprises Ti-(45-48)Al-(1-10)M (at. Xtrace amount %), with M being at least one element from: V, Cr, Mn, Nb,Ta, W, and Mo, and with trace amounts of 0.1-5% of Si, B, and/or Mg. Insome embodiments, TiAl is a single-phase alloy γ(TiAl). In someembodiments, TiAl is a two-phase alloy γ(TiAl)+α2(Ti3Al). Single-phase γalloys contain third alloying elements such as Nb or Ta that promotestrengthening and additionally enhance oxidation resistance. The role ofthe third alloying elements in the two-phase alloys is to raiseductility (V, Cr, Mn), oxidation resistance (Nb, Ta) or combinedproperties. Additions such as Si, B, and Mg can markedly enhance otherproperties. The thicknesses of the layers of capacitor 1500 in thex-axis are in the range of 1 nm to 30 nm. In some embodiment, refractiveinter-metallic layers are not used for non-planar capacitor structure1500.

FIG. 15B illustrates non-planar linear capacitor structure 1520 withoutconductive oxides, in accordance with some embodiments. Compared to FIG.15A, here the linear dielectric is adjacent to the top electrode and thebottom electrode.

FIG. 16A illustrates multi-input capacitive circuit 1600 with stackedplanar capacitor structure, wherein the multi-input capacitive circuitincludes a pull-up device, in accordance with some embodiments. In thisexample, pull-up device is shown which is controlled by the Up controlon its gate terminal. The source and drain terminals of transistor MP1is coupled to contact (CA). Etch stop layer is used in the fabricationof vias (via0) to connect the source or drain of the transistors tosumming node n1 on metal-1 (M1) layer. Another etch stop layer is formedover M1 layer to fabricate vias (vial) to couple to respective M1layers. In some embodiments, metal-2 (M2) is deposited over vias (vial).M2 layer is then polished. In some embodiments, the capacitor can bemoved further up in the stack, where the capacitor level processing isdone between different layers.

In some embodiments, oxide is deposited over the etch stop layer.Thereafter, dry, or wet etching is performed to form holes forpedestals. The holes are filled with metal and land on the respective M2layers. Fabrication processes such as interlayer dielectric (ILD) oxidedeposition followed by ILD etch (to form holes for the pedestals),deposition of metal into the holes, and subsequent polishing of thesurface are used to prepare for post pedestal fabrication.

A number of fabrication processes of deposition, lithography, andetching takes place to form the stack of layers for the planarcapacitor. In some embodiments, the linear dielectric capacitors areformed in a backend of the die. In some embodiments, deposition of ILDis followed by surface polish. In some embodiments, a metal layer isformed over top electrode of each capacitor to connect to a respectiveinput. For example, metal layer over the top electrode of capacitor C1is connected to input ‘a’. Metal layer over the top electrode ofcapacitor C2 is connected to input ‘b’. Metal layer over the topelectrode of capacitor C3 is connected to input ‘c’. Metal layer overthe top electrode of capacitor C4 is connected to input ‘d’. The metallayers coupled to the bottom electrodes of capacitors C1, C2, C3, and C4are coupled to summing node n1 through respective vias.

In this case, after polishing the surface, ILD is deposited, inaccordance with some embodiments. Thereafter, holes are etched throughthe ILD to expose the top electrodes of the capacitors, in accordancewith some embodiments. The holes are then filled with metal, inaccordance with some embodiments. Followed by filling the holes, the topsurface is polished, in accordance with some embodiments. As such, thecapacitors are connected to input electrode (e.g., input ‘a’, input ‘b’,input ‘c’, and input ‘d’) and summing node n1 (through the pedestals),in accordance with some embodiments.

In some embodiments, ILD is deposited over the polished surface. Holesfor via are then etched to contact the M2 layer, in accordance with someembodiments. The holes are filled with metal to form vias (via2), inaccordance with some embodiments. The top surface is then polished, inaccordance with some embodiments. In some embodiments, process ofdepositing metal over the vias (via2), depositing ILD, etching holes toform pedestals for the next capacitors of the stack, forming thecapacitors, and then forming vias that contact the M3 layer arerepeated. This process is repeated ‘n’ times for forming ‘n’ capacitorsin a stack for ‘n’ number of inputs, in accordance with someembodiments.

In some embodiments, the bottom electrode of each capacitor is allowedto directly contact with the metal below. For example, the pedestalsthat connect to the top and bottom electrodes are removed. In thisembodiment, the height of the stacked capacitors is lowered, and thefabrication process is simplified because the extra steps for formingthe pedestals are removed.

In some embodiments, pedestals or vias are formed for both the top andbottom electrodes of the planar capacitors. In this embodiment, theheight of the stacked capacitors is raised, and the fabrication processadds an additional step of forming a top pedestal or via which contactswith respective input electrodes (e.g., input ‘a’, input ‘b’, input ‘c’,and input ‘d’).

FIG. 16B illustrates multi-input capacitive circuit 1620 with stackedplanar capacitor structure, wherein the multi-input capacitive circuitincludes a pull-down device, in accordance with some embodiments.Multi-input capacitive circuit 1620 is like multi-input capacitivecircuit 1600, but with pull-down device MN1. Here, pull-up device MP1 isremoved from the summing node.

FIG. 17A illustrates multi-input capacitive circuit 1700 with stackednon-planar capacitor structure wherein the multi-input capacitivecircuit includes a pull-up device, in accordance with some embodiments.In this example four capacitors are stacked. In some embodiments, acolumn of shared metal passes through the center of the capacitors,where the shared metal is the summing node n1 which is coupled to thestub and then to the source or drain terminals of the pull-up (MP1)transistor. Top electrode of each of the capacitor is partially adjacentto a respective input electrode. For example, the top electrode ofcapacitor C1 is coupled to input electrode ‘a’, the top electrode ofcapacitor C2 is coupled to input electrode ‘b’, the top electrode ofcapacitor C3 is coupled to input electrode ‘c’, and the top electrode ofcapacitor C4 is coupled to input electrode ‘d’. In this instance, thecapacitors are formed between regions reserved for Via1 through Via5(e.g., between M1 through M6 layers). The capacitors here can becapacitors with linear dielectric or capacitors with paraelectricdielectric.

FIG. 17B illustrates multi-input capacitive circuit 1720 with stackednon-planar capacitor structure wherein the multi-input capacitivecircuit includes a pull-down device, in accordance with someembodiments. Multi-input capacitive circuit 1720 is like multi-inputcapacitive circuit 1700, but with pull-down device MN1. Here, pull-updevice MP1 is removed from the summing node. The capacitors here cancomprise linear dielectric or paraelectric material.

FIG. 18A illustrates planar ferroelectric or paraelectric capacitorstructure 1800, in accordance with some embodiments. In someembodiments, capacitors for the multi-input capacitive structures areferroelectric capacitors. These capacitors can take any planar form. Onesuch simplified form is illustrated in FIG. 18A. Here, planar capacitorstructure 1800 is a metal-insulator-metal (MIM) capacitor comprising abottom electrode, a top electrode, and a ferroelectric dielectricbetween the top electrode and the bottom electrode as shown. In someembodiments, conductive oxide layer(s) are formed between the bottomelectrode and the ferroelectric dielectric.

FIG. 18B illustrates three planar ferroelectric or paraelectriccapacitor structures, respectively, in accordance with some embodiments.Here, any one of the three planar capacitor structures 1823 a, 1823 b,and 1823 c is represented by the simplified planar capacitor structure1800.

In some embodiments, planar capacitor 1823 a incudes encapsulationportions 1821 a and 1821 b that are adjacent to the side walls of theplurality of layers of the planar capacitor. In some embodiments, planarcapacitor 1823 b incudes encapsulation portions 1821 c and 1821 d thatare partially adjacent to sidewall barrier seal 1821 a and 1821 b, andrefractive inter-metallic layers 1811 a. In various embodiments,encapsulation portions 1821 c and 1821 d terminate into a via (notshown). The material for encapsulation portions 1821 c and 1821 d issame as those for sidewall barrier seal 1821 a and 1821 b. In someembodiments, the barrier material includes one or more of an oxide of:Ti, Al, or Mg.

In some embodiments, planar capacitor 1823 c includes encapsulationportions 1821 e and 1821 f that are partially adjacent to sidewallbarrier seal 1821 a and 1821 b, and refractive inter-metallic layers1811 b. In various embodiments, encapsulation portions 1821 e and 1821 fterminate into a via (not shown). The material for encapsulationportions 1821 e and 1821 f is same as those for sidewall barrier seal1821 a and 1821 b. Material for 1812 a and 1821 b includes one or moreof: Ti—Al—O, Al2O3, MgO, or nitride. Material for 1812 a and 1821 b is asidewall barrier (e.g., insulative material) that protects the stack oflayers from hydrogen and/or oxygen diffusion. In various embodiments,the sidewall barrier material is not an interlayer dielectric (ILD)material. In some embodiments, the lateral thickness (along x-axis) ofthe sidewall barrier seal 1821 a/b (insulating material) is in a rangeof 0.1 nm to 20 nm. In some embodiments, sidewall barriers are in directcontact with ILD.

In some embodiments, planar capacitors 1823 a, 1823 b, and 1823 ccomprise a number of layers stacked together to form a planar capacitor.These layers may be extending in an x-plane when the capacitor is aplanar capacitor. In some embodiments, the stack of layers includesrefractive inter-metallic 1811 a/b as a barrier material; conductiveoxides 1812 a/b, and FE material 1813. FE material 1813 can be any ofthe FE materials discussed herein. In some embodiments, refractiveinter-metallic 1811 a/b are removed, and electrodes are in directcontact with conductive oxides 1812 a/b.

In some embodiments, refractive inter-metallic 1811 a/b maintains the FEproperties of the FE capacitor. In the absence of refractiveinter-metallic 1811 a/b, the ferroelectric material 1813 of thecapacitor may lose its potency. In some embodiments, refractiveinter-metallic 1811 a/b comprises Ti and Al (e.g., TiAl compound). Insome embodiments, refractive inter-metallic 1811 a/b comprises one ormore of Ta, W, and/or Co. For example, refractive inter-metallic 1811a/b includes a lattice of Ta, W, and Co.

In some embodiments, refractive inter-metallic 1811 a/b is part of abarrier layer which is a super lattice of a first material and a secondmaterial, wherein the first material includes Ti and Al (e.g., TiAl) andthe second material includes Ta, W, and Co (e.g., layers of Ta, W, andCo together). In various embodiments, the lattice parameters of thebarrier layer are matched with the lattice parameters of the conductiveoxides and/or FE material 1813.

In some embodiments, refractive inter-metallic 1811 a/b includes one of:Ti—Al such as Ti3Al, TiAl, TiAl3; Ni—Al such as Ni3Al, NiAl3, NiAl;Ni—Ti, Ni—Ga, Ni2MnGa; FeGa, Fe3Ga; borides, carbides, or nitrides. Insome embodiments, TiAl material comprises Ti-(45-48)Al-(1-10)M (at. Xtrace amount %), with M being at least one element from: V, Cr, Mn, Nb,Ta, W, and Mo, and with trace amounts of 0.1-5% of Si, B, and/or Mg. Insome embodiments, TiAl is a single-phase alloy γ(TiAl). In someembodiments, TiAl is a two-phase alloy γ(TiAl)+α2(Ti3Al). Single-phase γalloys contain third alloying elements such as Nb or Ta that promotestrengthening and additionally enhance oxidation resistance. The role ofthe third alloying elements in the two-phase alloys is to raiseductility (V, Cr, Mn), oxidation resistance (Nb, Ta) or combinedproperties. Additions such as Si, B, and Mg can markedly enhance otherproperties. In some embodiments, barrier layer 1811 a is coupled to atop electrode. In some embodiments, sidewall barrier seal 1821 a/b(insulating material) is placed around layers 1811 a, 1812 a, 1813, 1812b, and 1811 b along while the top and bottom surfaces of 1811 a and 1811b are exposed for coupling to metal layers, vias, or a metallicpedestal.

In some embodiments, conductive oxide layer(s) are formed between thetop electrode and the ferroelectric dielectric. Examples of conductiveoxides include: IrO₂, RuO₂, PdO₂, OsO₂, or ReO₃. In some examples,conductive oxides are of the form A2O3 (e.g., In2O3, Fe2O3) and ABO3type, where ‘A’ is a rare earth element and B is Mn.

Any suitable conductive material may be used for the top electrode andthe bottom electrode. For example, the material or the electrode mayinclude one or more of: Cu, Al, Ag, Au, W, or Co. In some embodiments,the thickness along the z-axis of the top electrode and bottom electrodeis in a range of 1 nm to 30 nm. In some embodiments, the thickness alongthe z-axis of the dielectric is in a range of 1 nm to 30 nm. In someembodiments, the thickness along the z-axis of the conductive oxide isin a range of 1 nm to 30 nm.

FIG. 19A illustrates non-planar ferroelectric or paraelectric capacitorstructure 1900, in accordance with some embodiments. In someembodiments, non-planar capacitor structure 1900 is rectangular inshape. Taking the cylindrical shaped case for example, in someembodiments, the layers of non-planar capacitor structure 1900 from thecenter going outwards include bottom electrode 1901 a, first conductiveoxide 1912 a, ferroelectric dielectric material 1913, second conductiveoxide 1912 b, and top electrode 1901 b. A cross-sectional view along the“ab” dashed line is illustrated in the middle of FIG. 19A. In someembodiments, conducting oxides are removed and the ferroelectricdielectric is directly connected to top electrode 1901 b and bottomelectrodes 1901 a. In some embodiments, ferroelectric dielectricmaterial 1913 can include any suitable dielectric, where the thicknessof dielectric film is a range of 1 nm to 20 nm. In some embodiments,ferroelectric dielectric material 1913 include any one of the materialsdiscussed herein for ferroelectrics.

In some embodiments, first conductive oxide 1912 a is conformallydeposited over bottom electrode 1901 a. In some embodiments, dielectricmaterial 1913 is conformally deposited over first conductive oxide 1912a. In some embodiments, second conductive oxide 1912 b is conformallydeposited over dielectric material 1913. In some embodiments, topelectrode 1901 b is conformally deposited over second conductive oxide1912 b. In some embodiments, bottom electrode 1901 a is in the centerwhile top electrode 1901 b is on an outer circumference of non-planarcapacitor structure 1900.

In some embodiments, material for bottom electrode 1901 a may includeone or more of: Cu, Al, Ag, Au, W, or Co, or their alloys. In someembodiments, material for first conductive oxide 1912 a include: IrO₂,RuO₂, PdO₂, OsO₂, or ReO₃. In some examples, conductive oxides are ofthe form Al2O3 (e.g., In2O3, Fe2O3) and ABO3 type, where ‘A’ is a rareearth element and B is Mn. In some embodiments, material for secondconductive oxide 1912 b may be same as the material for first conductiveoxide 1912 a. In some embodiments, material for top electrode 1901 b mayinclude one or more of: Cu, Al, Ag, Au, W, or Co, or their alloys.

In some embodiments, a first refractive inter-metallic layer (not shown)is formed between dielectric material 1913 and first conductive oxide1912 a. In some embodiments, a second refractive inter-metallic layer(not shown) is formed between dielectric capacitor material 1913 andsecond conductive oxide 1912 b. In these cases, the first and secondrefractive inter-metallic layers are directly adjacent to theirrespective conductive oxide layers and to dielectric capacitor material1913. In some embodiments, refractive inter-metallic maintains thecapacitive properties of the dielectric capacitor material 1913. In someembodiments, refractive inter-metallic comprises Ti and Al (e.g., TiAlcompound). In some embodiments, refractive inter-metallic comprises oneor more of Ta, W, and/or Co.

For example, refractive inter-metallic includes a lattice of Ta, W, andCo. In some embodiments, refractive inter-metallic includes one of:Ti-Al such as Ti3Al, TiAl, TiAl3; Ni—Al such as Ni3Al, NiAl3, NiAl;Ni—Ti, Ni—Ga, Ni2MnGa; FeGa, Fe3Ga; borides, carbides, or nitrides. Insome embodiments, TiAl material comprises Ti-(45-48)Al-(1-10)M (at. Xtrace amount %), with M being at least one element from: V, Cr, Mn, Nb,Ta, W, and Mo, and with trace amounts of 0.1-5% of Si, B, and/or Mg. Insome embodiments, TiAl is a single-phase alloy γ(TiAl). In someembodiments, TiAl is a two-phase alloy γ(TiAl)+α2(Ti3Al). Single-phase yalloys contain third alloying elements such as Nb or Ta that promotestrengthening and additionally enhance oxidation resistance. The role ofthe third alloying elements in the two-phase alloys is to raiseductility (V, Cr, Mn), oxidation resistance (Nb, Ta) or combinedproperties. Additions such as Si, B and Mg can markedly enhance otherproperties. The thicknesses of the layers of capacitor 1900 in thex-axis are in the range of 1 nm to 30 nm. In some embodiment, refractiveinter-metallic layers are not used for non-planar capacitor structure1900.

FIG. 19B illustrates non-planar ferroelectric or paraelectric capacitorstructure 1920 without conductive oxides, in accordance with someembodiments. Compared to non-planar capacitor structure 1900, here firstconductive oxide 1912 a and second conductive oxide 1912 b are removedand ferroelectric material 1913 is adjacent to top electrode 1901 b andbottom electrode 1910 a as shown.

FIG. 20 illustrates multi-input capacitive circuit 2000 with stackedplanar ferroelectric or paraelectric capacitor structure, wherein themulti-input capacitive circuit includes a pull-up device and a pull-downdevice, in accordance with some embodiments. In this example, twotransistors are shown, each controlled by its respective Up or Downcontrols on its gate terminal. The source and drain terminals of eachtransistor is coupled to respective contacts (CA). Etch stop layer isused in the fabrication of vias (via0) to connect the source or drain ofthe transistors to summing node n1 on metal-1 (M1) layer. Another etchstop layer is formed over M1 layer to fabricate vias (via1) to couple torespective M1 layers. In some embodiments, metal-2 (M2) is depositedover vias (via1). M2 layer is then polished. In some embodiments, theferroelectric capacitor can be moved further up in the stack, where thecapacitor level processing is done between different layers.

In some embodiments, oxide is deposited over the etch stop layer.Thereafter, dry, or wet etching is performed to form holes forpedestals. The holes are filled with metal and land on the respective M2layers. Fabrication processes such as interlayer dielectric (ILD) oxidedeposition followed by ILD etch (to form holes for the pedestals),deposition of metal into the holes, and subsequent polishing of thesurface are used to prepare for post pedestal fabrication.

A number of fabrication processes of deposition, lithography, andetching takes place to form the stack of layers for the planarcapacitor. In some embodiments, the ferroelectric dielectric capacitorsare formed in a backend of the die. In some embodiments, deposition ofILD is followed by surface polish. In some embodiments, a metal layer isformed over top electrode of each capacitor to connect to a respectiveinput. For example, metal layer over the top electrode of capacitor C1is connected to input ‘a’. Metal layer over the top electrode ofcapacitor C2 is connected to input ‘b’. Metal layer over the topelectrode of capacitor C3 is connected to input ‘c’. Metal layer overthe top electrode of capacitor C4 is connected to input ‘d’. The metallayers coupled to the bottom electrodes of capacitors C1, C2, C3, and C4are coupled to summing node n1 through respective vias.

In this case, after polishing the surface, ILD is deposited, inaccordance with some embodiments. Thereafter, holes are etched throughthe ILD to expose the top electrodes of the capacitors, in accordancewith some embodiments. The holes are then filled with metal, inaccordance with some embodiments. Followed by filling the holes, the topsurface is polished, in accordance with some embodiments. As such, thecapacitors are connected to input electrode (e.g., input ‘a’, input ‘b’,input ‘c’, and input ‘d’) and summing node n1 (through the pedestals),in accordance with some embodiments.

In some embodiments, ILD is deposited over the polished surface. Holesfor via are then etched to contact the M2 layer, in accordance with someembodiments. The holes are filled with metal to form vias (via2), inaccordance with some embodiments. The top surface is then polished, inaccordance with some embodiments. In some embodiments, process ofdepositing metal over the vias (via2), depositing ILD, etching holes toform pedestals for the next capacitors of the stack, forming thecapacitors, and then forming vias that contact the M3 layer arerepeated. This process is repeated ‘n’ times for forming ‘n’ capacitorsin a stack for ‘n’ number of inputs, in accordance with someembodiments.

In some embodiments, the bottom electrode of each capacitor is allowedto directly contact with the metal below. For example, the pedestalsthat connect to the top and bottom electrodes are removed. In thisembodiment, the height of the stacked capacitors is lowered, and thefabrication process is simplified because the extra steps for formingthe pedestals are removed.

In some embodiments, pedestals or vias are formed for both the top andbottom electrodes of the planar capacitors. In this embodiment, theheight of the stacked capacitors is raised, and the fabrication processadds an additional step of forming a top pedestal or via which contactswith respective input electrodes (e.g., input ‘a’, input ‘b’, input ‘c’,and input ‘d’).

FIG. 21 illustrates multi-input capacitive circuit 2100 with stackednon-planar ferroelectric or paraelectric capacitor structure (e.g.,structures of FIG. 18A or FIG. 18B), wherein the multi-input capacitivecircuit includes a pull-down device and a pull-up device, in accordancewith some embodiments. In this example four capacitors are stacked. Insome embodiments, a column of shared metal passes through the center ofthe capacitors, where the shared metal is the summing node n1 which iscoupled to the stub and then to the source or drain terminals of thepull-up (MP1) and pull-down (MN1) transistors. Top electrode of each ofthe capacitor is partially adjacent to a respective input electrode. Forexample, the top electrode of capacitor C1 is coupled to input electrode‘a’, the top electrode of capacitor C2 is coupled to input electrode‘b’, the top electrode of capacitor C3 is coupled to input electrode‘c’, and the top electrode of capacitor C4 is coupled to input electrode‘d’. In this instance, the capacitors are formed between regionsreserved for Via1 through Via5 (e.g., between M1 through M6 layers).

FIG. 22 illustrates a high-level architecture of an artificialintelligence (AI) machine 2200 comprising a compute die stacked with amemory die, wherein the compute die includes a c-element, completiontree, and/or validity tree with a multi-input capacitive circuit withconfigurable threshold, in accordance with some embodiments.

AI machine 2200 comprises computational block 2201 or processor havingrandom-access memory (RAM) 2202 and computational logic 2203; firstrandom-access memory 2204 (e.g., static RAM (SRAM), ferroelectric orparaelectric RAM (FeRAM), ferroelectric or paraelectric staticrandom-access memory (FeSRAM)), main processor 2205, secondrandom-access memory 2206 (dynamic RAM (DRAM), FeRAM), and solid-statememory or drive (SSD) 2207. In some embodiments, some, or all componentsof AI machine 2200 are packaged in a single package forming asystem-on-chip (SoC). The SoC can be configured as a logic-on-logicconfiguration, which can be in a 3D configuration or a 2.5Dconfiguration.

In some embodiments, computational block 2201 is packaged in a singlepackage and then coupled to processor 2205 and memories 2204, 2206, and2207 on a printed circuit board (PCB). In some embodiments,computational block 2201 is configured as a logic-on-logicconfiguration, which can be in a 3D configuration or a 2.5Dconfiguration. In some embodiments, computational block 2201 comprises aspecial purpose compute die 2203 or microprocessor. For example, computedie 2203 is a compute chiplet that performs a function of an acceleratoror inference. In some embodiments, memory 2202 is DRAM which forms aspecial memory/cache for the special purpose compute die 2203. The DRAMcan be embedded DRAM (eDRAM) such as 1T1C (one transistor and onecapacitor) based memories. In some embodiments, RAM 2202 isferroelectric or paraelectric RAM (Fe-RAM).

In some embodiments, compute die 2203 is specialized for applicationssuch as Artificial Intelligence, graph processing, and algorithms fordata processing. In some embodiments, compute die 2203 further has logiccomputational blocks, for example, for multipliers and buffers, aspecial data memory block (e.g., buffers) comprising DRAM, FeRAM, or acombination of them. In some embodiments, RAM 2202 has weights andinputs stored to improve the computational efficiency. The interconnectsbetween processor 2205 (also referred to as special purpose processor),first RAM 2204 and compute die 2203 are optimized for high bandwidth andlow latency. The architecture of FIG. 22 allows efficient packaging tolower the energy, power, or cost and provides for ultra-high bandwidthbetween RAM 2202 and compute chiplet 2203 of computational block 2201.

In some embodiments, RAM 2202 is partitioned to store input data (ordata to be processed) 2202 a and weight factors 2202 b. In someembodiments, input data 2202 a is stored in a separate memory (e.g., aseparate memory die) and weight factors 2202 b are stored in a separatememory (e.g., separate memory die).

In some embodiments, computational logic or compute chiplet 2203comprises matrix multiplier, adder, concatenation logic, buffers, andcombinational logic. In various embodiments, compute chiplet 2203performs multiplication operation on inputs 2202 a and weights 2202 b.In some embodiments, weights 2202 b are fixed weights. For example,processor 2205 (e.g., a graphics processor unit (GPU), fieldprogrammable grid array (FPGA) processor, application specificintegrated circuit (ASIC) processor, digital signal processor (DSP), anAI processor, a central processing unit (CPU), or any otherhigh-performance processor) computes the weights for a training model.Once the weights are computed, they are stored in memory 2202. Invarious embodiments, the input data that is to be analyzed using atrained model, is processed by computational block 2201 with computedweights 2202 b to generate an output (e.g., a classification result).

In some embodiments, first RAM 2204 is ferroelectric or paraelectricbased SRAM. For example, a six transistor (6T) SRAM bit-cells havingferroelectric or paraelectric transistors are used to implement anon-volatile FeSRAM. In some embodiments, SSD 2207 comprises NAND flashcells. In some embodiments, SSD 2207 comprises NOR flash cells. In someembodiments, SSD 2207 comprises multi-threshold NAND flash cells.

In various embodiments, the non-volatility of FeRAM is used to introducenew features such as security, functional safety, and faster reboot timeof AI machine 2200. The non-volatile FeRAM is a low power RAM thatprovides fast access to data and weights. FeRAM 2204 can also serve as afast storage for computational block 2201 (which can be an inference dieor an accelerator), which typically has low capacity and fast accessrequirements.

In various embodiments, FeRAM (FeDRAM or FeSRAM) includes ferroelectricor paraelectric material. The ferroelectric or paraelectric material maybe in a transistor gate stack or in a capacitor of the memory. Theferroelectric material can be any suitable low voltage FE materialdiscussed with reference to various embodiments. While embodiments hereare described with reference to ferroelectric material, the embodimentsare applicable to any of the nonlinear polar materials described herein.

FIG. 23 illustrates an architecture of a computational block 2300comprising a compute die stacked with a memory die, wherein the computedie includes a c-element, completion tree, and/or validity tree with amulti-input capacitive circuit with configurable threshold, inaccordance with some embodiments. The architecture of FIG. 23illustrates an architecture for a special purpose compute die where RAMmemory buffers for inputs and weights are split on die-1 and logic andoptional memory buffers are split on die-2.

In some embodiments, memory die (e.g., Die 1) is positioned below acompute die (e.g., Die 2) such that a heat sink or thermal solution isadjacent to the compute die. In some embodiments, the memory die isembedded in an interposer. In some embodiments, the memory die behavesas an interposer in addition to its basic memory function. In someembodiments, the memory die is a high bandwidth memory (HBM) whichcomprises multiple dies of memories in a stack and a controller tocontrol the read and write functions to the stack of memory dies. Insome embodiments, the memory die comprises a first die 2301 to storeinput data and a second die 2302 to store weight factors. In someembodiments, the memory die is a single die that is partitioned suchthat first partition 2301 of the memory die is used to store input dataand second partition 2302 of the memory die is used to store weights. Insome embodiments, the memory die comprises DRAM. In some embodiments,the memory die comprises FE-SRAM or FE-DRAM. In some embodiments, thememory die comprises MRAM. In some embodiments, the memory die comprisesSRAM. For example, memory partitions 2301 and 2302, or memory dies 2301and 2302 include one or more of: DRAM, FE-SRAM, FE-DRAM, SRAM, and/orMRAM. In some embodiments, the input data stored in memory partition ordie 2301 is the data to be analyzed by a trained model with fixedweights stored in memory partition or die 2302.

In some embodiments, the compute die comprises ferroelectric orparaelectric logic (e.g., majority, minority, and/or threshold gates) toimplement matrix multiplier 2303, logic 2304, and temporary buffer 2305.Matrix multiplier 2303 performs multiplication operation on input data‘X’ and weights ‘W’ to generate an output ‘Y’. This output may befurther processed by logic 2304. In some embodiments, logic 2304performs a threshold operation, pooling and drop out operations, and/orconcatenation operations to complete the AI logic primitive functions.

In some embodiments, the output of logic 2304 (e.g., processed output‘Y’) is temporarily stored in buffer 2305. In some embodiments, buffer2305 is memory such as one or more of: DRAM, Fe-SRAM, Fe-DRAM, MRAM,resistive RAM (Re-RAM) and/or SRAM. In some embodiments, buffer 2305 ispart of the memory die (e.g., Die 1). In some embodiments, buffer 2305performs the function of a re-timer. In some embodiments, the output ofbuffer 2305 (e.g., processed output ‘Y’) is used to modify the weightsin memory partition or die 2302. In one such embodiment, computationalblock 2300 not only operates as an inference circuitry, but also as atraining circuitry to train a model. In some embodiments, matrixmultiplier 2303 includes an array of multiplier cells, wherein the DRAMs2301 and 2302 include arrays of memory bit-cells, respectively, whereineach multiplier cell is coupled to a corresponding memory bit-cell ofDRAM 2301 and/or DRAM 2302. In some embodiments, computational block2300 comprises an interconnect fabric coupled to the array of multipliercells such that each multiplier cell is coupled to the interconnectfabric.

Architecture 2300 provides reduced memory access for the compute die(e.g., die 2) by providing data locality for weights, inputs, andoutputs. In one example, data from and to the AI computational blocks(e.g., matrix multiplier 2303) is locally processed within a samepackaging unit. Architecture 2300 also segregates the memory and logicoperations onto a memory die (e.g., Die 1) and a logic die (e.g., Die2), respectively, allowing for optimized AI processing. Desegregateddies allow for improved yield of the dies. A high-capacity memoryprocess for Die 1 allows reduction of power of the externalinterconnects to memory, reduces cost of integration, and results in asmaller footprint.

FIG. 24 illustrates a system-on-chip (SOC) 2400 that uses a c-element,completion tree, and/or validity tree with a multi-input capacitivecircuit with configurable threshold, in accordance with someembodiments. SoC 2400 comprises memory 2401 having static random-accessmemory (SRAM) or FE based random-access memory FE-RAM, or any othersuitable memory. The memory can be non-volatile (NV) or volatile memory.Memory 2401 may also comprise logic 2403 to control memory 2402. Forexample, write and read drivers are part of logic 2403. These driversand other logic are implemented using the majority or threshold gates ofvarious embodiments. The logic can comprise majority or threshold gatesand traditional logic (e.g., CMOS based NAND, NOR etc.).

SoC further comprises a memory I/O (input-output) interface 2404. Theinterface may be a double-data rate (DDR) compliant interface or anyother suitable interface to communicate with a processor. Processor 2405of SoC 2400 can be a single core or multiple core processor. Processor2405 can be a general-purpose processor (CPU), a digital signalprocessor (DSP), or an Application Specific Integrated Circuit (ASIC)processor. In some embodiments, processor 2405 is an artificialintelligence (AI) processor (e.g., a dedicated AI processor, a graphicsprocessor configured as an AI processor). In various embodiments,processor 2405 executes instructions that are stored in memory 2401.

AI is a broad area of hardware and software computations where data isanalyzed, classified, and then a decision is made regarding the data.For example, a model describing classification of data for a certainproperty or properties is trained over time with large amounts of data.The process of training a model requires large amounts of data andprocessing power to analyze the data. When a model is trained, weightsor weight factors are modified based on outputs of the model. Onceweights for a model are computed to a high confidence level (e.g., 95%or more) by repeatedly analyzing data and modifying weights to get theexpected results, the model is deemed “trained.” This trained model withfixed weights is then used to make decisions about new data. Training amodel and then applying the trained model for new data is hardwareintensive activity. In some embodiments, the AI processor has reducedlatency of computing the training model and using the training model,which reduces the power consumption of such AI processor systems.

Processor 2405 may be coupled to a number of other chiplets that can beon the same die as SoC 2400 or on separate dies. These chiplets includeconnectivity circuitry 2406, I/O controller 2407, power management 2408,and display system 2409, and peripheral connectivity 2406.

Connectivity 2406 represents hardware devices and software componentsfor communicating with other devices. Connectivity 2406 may supportvarious connectivity circuitries and standards. For example,connectivity 2406 may support GSM (global system for mobilecommunications) or variations or derivatives, CDMA (code divisionmultiple access) or variations or derivatives, TDM (time divisionmultiplexing) or variations or derivatives, 3rd Generation PartnershipProject (3GPP) Universal Mobile Telecommunications Systems (UMTS) systemor variations or derivatives, 3GPP Long-Term Evolution (LTE) system orvariations or derivatives, 3GPP LTE-Advanced (LTE-A) system orvariations or derivatives, Fifth Generation (5G) wireless system orvariations or derivatives, 5G mobile networks system or variations orderivatives, 5G New Radio (NR) system or variations or derivatives, orother cellular service standards. In some embodiments, connectivity 2406may support non-cellular standards such as WiFi.

I/O controller 2407 represents hardware devices and software componentsrelated to interaction with a user. I/O controller 2407 is operable tomanage hardware that is part of an audio subsystem and/or displaysubsystem. For example, input through a microphone or other audio devicecan provide input or commands for one or more applications or functionsof SoC 2400. In some embodiments, I/O controller 2407 illustrates aconnection point for additional devices that connect to SoC 2400 throughwhich a user might interact with the system. For example, devices thatcan be attached to the SoC 2400 might include microphone devices,speaker or stereo systems, video systems or other display devices,keyboard or keypad devices, or other I/O devices for use with specificapplications such as card readers or other devices.

Power management 2408 represents hardware or software that performspower management operations, e.g., based at least in part on receivingmeasurements from power measurement circuitries, temperature measurementcircuitries, charge level of battery, and/or any other appropriateinformation that may be used for power management. By using majority andthreshold gates of various embodiments, non-volatility is achieved atthe output of these logic. Power management 2408 may accordingly putsuch logic into low power state without the worry of losing data. Powermanagement may select a power state according to Advanced Configurationand Power Interface (ACPI) specification for one or all components ofSoC 2400.

Display system 2409 represents hardware (e.g., display devices) andsoftware (e.g., drivers) components that provide a visual and/or tactiledisplay for a user to interact with the processor 2405. In someembodiments, display system 2409 includes a touch screen (or touch pad)device that provides both output and input to a user. Display system2409 may include a display interface, which includes the particularscreen or hardware device used to provide a display to a user. In someembodiments, the display interface includes logic separate fromprocessor 2405 to perform at least some processing related to thedisplay.

Peripheral connectivity 2410 may represent hardware devices and/orsoftware devices for connecting to peripheral devices such as printers,chargers, cameras, etc. In some embodiments, peripheral connectivity2410 may support communication protocols, e.g., PCIe (PeripheralComponent Interconnect Express), USB (Universal Serial Bus),Thunderbolt, High-Definition Multimedia Interface (HDMI), Firewire, etc.

In various embodiments, SoC 2400 includes a coherent cache ormemory-side buffer chiplet (not shown) which include ferroelectric orparaelectric memory. The coherent cache or memory-side buffer chipletcan be coupled to processor 2405 and/or memory 2401 according to thevarious embodiments described herein (e.g., via silicon bridge orvertical stacking).

The term “device” may generally refer to an apparatus according to thecontext of the usage of that term. For example, a device may refer to astack of layers or structures, a single structure or layer, a connectionof various structures having active and/or passive elements, etc.Generally, a device is a three-dimensional structure with a plane alongthe x-y direction and a height along the z direction of an x-y-zCartesian coordinate system. The plane of the device may also be theplane of an apparatus, which comprises the device.

Throughout the specification, and in the claims, the term “connected”means a direct connection, such as electrical, mechanical, or magneticconnection between the things that are connected, without anyintermediary devices.

The term “coupled” means a direct or indirect connection, such as adirect electrical, mechanical, or magnetic connection between the thingsthat are connected or an indirect connection, through one or morepassive or active intermediary devices.

The term “adjacent” here generally refers to a position of a thing beingnext to (e.g., immediately next to or close to with one or more thingsbetween them) or adjoining another thing (e.g., abutting it).

The term “circuit” or “module” may refer to one or more passive and/oractive components that are arranged to cooperate with one another toprovide a desired function.

The term “signal” may refer to at least one current signal, voltagesignal, magnetic signal, or data/clock signal. The meaning of “a,” “an,”and “the” include plural references. The meaning of “in” includes “in”and “on.”

Here, the term “analog signal” generally refers to any continuous signalfor which the time varying feature (variable) of the signal is arepresentation of some other time varying quantity, i.e., analogous toanother time varying signal.

Here, the term “digital signal” generally refers to a physical signalthat is a representation of a sequence of discrete values (a quantifieddiscrete-time signal), for example of an arbitrary bit stream, or of adigitized (sampled and analog-to-digital converted) analog signal.

The term “scaling” generally refers to converting a design (schematicand layout) from one process technology to another process technologyand subsequently being reduced in layout area. The term “scaling”generally also refers to downsizing layout and devices within the sametechnology node. The term “scaling” may also refer to adjusting (e.g.,slowing down or speeding up—i.e., scaling down, or scaling uprespectively) of a signal frequency relative to another parameter, forexample, power supply level.

The terms “substantially,” “close,” “approximately,” “near,” and“about,” generally refer to being within +/−10% of a target value. Forexample, unless otherwise specified in the explicit context of theiruse, the terms “substantially equal,” “about equal” and “approximatelyequal” mean that there is no more than incidental variation betweenamong things so described. In the art, such variation is typically nomore than +/−10% of a predetermined target value.

Unless otherwise specified the use of the ordinal adjectives “first,”“second,” and “third,” etc., to describe a common object, merelyindicate that different instances of like objects are being referred toand are not intended to imply that the objects so described must be in agiven sequence, either temporally, spatially, in ranking or in any othermanner.

For the purposes of the present disclosure, phrases “A and/or B” and “Aor B” mean (A), (B), or (A and B). For the purposes of the presentdisclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B),(A and C), (B and C), or (A, B and C).

The terms “left” “right,” “front,” “back,” “top,” “bottom,” “over,”“under,” and the like in the description and in the claims, if any, areused for descriptive purposes and not necessarily for describingpermanent relative positions. For example, the terms “over,” “under,”“front side,” “back side,” “top,” “bottom,” “over,” “under,” and “on” asused herein refer to a relative position of one component, structure, ormaterial with respect to other referenced components, structures ormaterials within a device, where such physical relationships arenoteworthy. These terms are employed herein for descriptive purposesonly and predominantly within the context of a device z-axis andtherefore may be relative to an orientation of a device. Hence, a firstmaterial “over” a second material in the context of a figure providedherein may also be “under” the second material if the device is orientedupside-down relative to the context of the figure provided. In thecontext of materials, one material disposed over or under another may bedirectly in contact or may have one or more intervening materials.Moreover, one material disposed between two materials may be directly incontact with the two layers or may have one or more intervening layers.In contrast, a first material “on” a second material is in directcontact with that second material. Similar distinctions are to be madein the context of component assemblies.

The term “between” may be employed in the context of the z-axis, x-axisor y-axis of a device. A material that is between two other materialsmay be in contact with one or both of those materials, or it may beseparated from both of the other two materials by one or moreintervening materials. A material “between” two other materials maytherefore be in contact with either of the other two materials, or itmay be coupled to the other two materials through an interveningmaterial. A device that is between two other devices may be directlyconnected to one or both of those devices, or it may be separated fromboth of the other two devices by one or more intervening devices.

Here, multiple non-silicon semiconductor material layers may be stackedwithin a single fin structure. The multiple non-silicon semiconductormaterial layers may include one or more “P-type” layers that aresuitable (e.g., offer higher hole mobility than silicon) for P-typetransistors. The multiple non-silicon semiconductor material layers mayfurther include one or more “N-type” layers that are suitable (e.g.,offer higher electron mobility than silicon) for N-type transistors. Themultiple non-silicon semiconductor material layers may further includeone or more intervening layers separating the N-type from the P-typelayers. The intervening layers may be at least partially sacrificial,for example to allow one or more of a gate, source, or drain to wrapcompletely around a channel region of one or more of the N-type andP-type transistors. The multiple non-silicon semiconductor materiallayers may be fabricated, at least in part, with self-aligned techniquessuch that a stacked CMOS device may include both a high-mobility N-typeand P-type transistor with a footprint of a single FET (field effecttransistor).

Here, the term “backend” generally refers to a section of a die which isopposite of a “frontend” and where an IC (integrated circuit) packagecouples to IC die bumps. For example, high-level metal layers (e.g.,metal layer 6 and above in a ten-metal stack die) and corresponding viasthat are closer to a die package are considered part of the backend ofthe die. Conversely, the term “frontend” generally refers to a sectionof the die that includes the active region (e.g., where transistors arefabricated) and low-level metal layers and corresponding vias that arecloser to the active region (e.g., metal layer 5 and below in theten-metal stack die example).

Reference in the specification to “an embodiment,” “one embodiment,”“some embodiments,” or “other embodiments” means that a particularfeature, structure, or characteristic described in connection with theembodiments is included in at least some embodiments, but notnecessarily all embodiments. The various appearances of “an embodiment,”“one embodiment,” or “some embodiments” are not necessarily allreferring to the same embodiments. If the specification states acomponent, feature, structure, or characteristic “may,” “might,” or“could” be included, that particular component, feature, structure, orcharacteristic is not required to be included. If the specification orclaim refers to “a” or “an” element, that does not mean there is onlyone of the elements. If the specification or claims refer to “anadditional” element, that does not preclude there being more than one ofthe additional elements.

Furthermore, the particular features, structures, functions, orcharacteristics may be combined in any suitable manner in one or moreembodiments. For example, a first embodiment may be combined with asecond embodiment anywhere the particular features, structures,functions, or characteristics associated with the two embodiments arenot mutually exclusive.

While the disclosure has been described in conjunction with specificembodiments thereof, many alternatives, modifications and variations ofsuch embodiments will be apparent to those of ordinary skill in the artin light of the foregoing description. The embodiments of the disclosureare intended to embrace all such alternatives, modifications, andvariations as to fall within the broad scope of the appended claims.

In addition, well-known power/ground connections to integrated circuit(IC) chips and other components may or may not be shown within thepresented figures, for simplicity of illustration and discussion, and soas not to obscure the disclosure. Further, arrangements may be shown inblock diagram form to avoid obscuring the disclosure, and also in viewof the fact that specifics with respect to implementation of such blockdiagram arrangements are highly dependent upon the platform within whichthe present disclosure is to be implemented (i.e., such specifics shouldbe well within purview of one skilled in the art). Where specificdetails (e.g., circuits) are set forth to describe example embodimentsof the disclosure, it should be apparent to one skilled in the art thatthe disclosure can be practiced without, or with variation of, thesespecific details. The description is thus to be regarded as illustrativeinstead of limiting.

The structures of various embodiments described herein can also bedescribed as method of forming those structures, and method of operationof these structures.

Following examples are provided that illustrate the various embodiments.The examples can be combined with other examples. As such, variousembodiments can be combined with other embodiments without changing thescope of the invention.

Example 1: An apparatus comprising: a first input; a second input; athird input; a control; a circuitry to adjust logic levels of the firstinput, the second input, and the control in a first operation mode; anda gate to receive the first input, the second input, and the thirdinput, wherein the third input is coupled to an output of the gate,wherein the gate comprises: a first capacitor having a first terminalcoupled to the first input, and a second terminal coupled to a summingnode; a second capacitor having a third terminal coupled to the secondinput, and a fourth terminal coupled to the summing node; a thirdcapacitor having a fifth terminal coupled to the third input, and asixth terminal coupled to the summing node; and a device coupled to thesumming node and a supply rail, wherein the device is controllable bythe control, wherein the circuitry is to adjust a function of the gatein the first operation mode, and wherein the circuitry is to allow thegate to operate in accordance with the function in a second operationmode.

Example 2: The apparatus of example 1, wherein the function is amajority function.

Example 3: The apparatus of example 1, wherein the first capacitor, thesecond capacitor, and the third capacitor comprise linear dielectricmaterial.

Example 4: The apparatus of example 3, wherein the linear dielectricmaterial includes one of: SiO2, Al2O3, Li2O, HfSiO4, Sc2O3, SrO, HfO2,ZrO2, Y2O3, Ta2O5, BaO, WO3, MoO3, or TiO2.

Example 5: The apparatus of example 1, wherein the device is a pull-updevice, wherein the circuitry is to set logic levels of the first input,the second input, and the third input to logic high, and the control toenable or turn on the pull-up device in the first operation mode toadjust a threshold of the gate to 2.

Example 6: The apparatus of example 1, wherein the first capacitor, thesecond capacitor, and the third capacitor include: a linear dielectricmaterial includes one or more of: Si, Al, Li, Hf, Sc, Sr, Zr, Y, Ta, Ba,W, Mo, or Ti; and a top electrode and a bottom electrode, wherein thelinear dielectric material is between the top electrode and the bottomelectrode, wherein the top electrode or the bottom electrode include oneor more of: Cu, Al, Ag, Au, W, or Co.

Example 7: The apparatus of example 1, wherein the first capacitor, thesecond capacitor, and the third capacitor include paraelectric materialwhich includes one of: SrTiO3, Ba(x)Sr(y)TiO3 (where x is −0.5, and y is0.95), HfZrO2, Hf—Si—O, BaTiO3, La-substituted PbTiO3, lead zirconatetitanate, or PMN-PT (lead magnesium niobate-lead titanate) based relaxorferroelectrics.

Example 8: The apparatus of example 1, wherein the first capacitor, thesecond capacitor, and the third capacitor include ferroelectricmaterial.

Example 9: The apparatus of example 1, wherein the device is a firstdevice, wherein the supply rail is a power supply rail, wherein thecontrol is a first control, wherein the gate comprises a second devicecoupled to the summing node and a ground supply rail, wherein the seconddevice is controllable by a second control.

Example 10: The apparatus of example 9, wherein, in the first operationmode, the circuitry is to adjust a threshold of the gate to 2 after thesecond device is enabled first, and then the second device is disabled,and then the first device is enabled, and the first input is set tologic 1, the second input is set to logic 1, and the third input is setto logic 0.

Example 11: The apparatus of example 9, wherein, in the first operationmode, the circuitry is to adjust a threshold of the gate to 2 after thefirst device is enabled first, and then the first device is disabled,and then the second device is enabled, and the first input is set tologic 1, the second input is set to logic 0, and the third input is setto logic 0.

Example 12: The apparatus of example 9, wherein the first capacitor, thesecond capacitor, and the third capacitor include ferroelectricmaterial, wherein the ferroelectric material includes one or more of:Bismuth ferrite (BFO), BFO with a doping material where in the dopingmaterial is one of Lanthanum, or elements from lanthanide series ofperiodic table; Lead zirconium titanate (PZT), or PZT with a dopingmaterial, wherein the doping material is one of La, Nb; a relaxorferroelectric which includes one of lead magnesium niobate (PMN), leadmagnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconatetitanate (PLZT), lead scandium niobate (PSN), Barium Titanium-BismuthZinc Niobium Tantalum (BT-BZNT), or Barium Titanium-Barium StrontiumTitanium (BT-BST); a perovskite which includes one of: BaTiO3, PbTiO3,KNbO3, or NaTaO3; a hexagonal ferroelectric which includes one of:YMnO3, or LuFeO3; hexagonal ferroelectrics of a type h-RMnO3, where R isa rare earth element which includes one of: cerium (Ce), dysprosium(Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho),lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr),promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium(Tm), ytterbium (Yb), or yttrium (Y); Hafnium (Hf), Zirconium (Zr),Aluminum (Al), Silicon (Si), their oxides or their alloyed oxides;Hafnium oxides as Hfl-x Ex 0y, where E can be Al, Ca, Ce, Dy, er, Gd,Ge, La, Sc, Si, Sr, Sn, or Y; Al(1-x)Sc(x)N, Ga(1-x)Sc(x)N, Al(1-x)Y(x)Nor Al(1-x-y)Mg(x)Nb(y)N, y doped HfO2, where x includes one of: Al, Ca,Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y, wherein ‘x’ is a fraction;Niobate type compounds LiNbO3, LiTaO3, Lithium iron Tantalum OxyFluoride, Barium Strontium Niobate, Sodium Barium Niobate, or Potassiumstrontium niobate; or an improper ferroelectric which includes one of:[PTO/STO]n or [LAO/STO]n, where ‘n’ is between 1 to 100.

Example 13: An apparatus comprising: a first input; a second input; athird input; a fourth input; a fifth input; and a gate to provide anoutput which is a consensus of the first input, the second input, andthe third input, wherein the gate receives the fourth input and thefifth input, wherein the output is coupled to the fourth input and thefifth input, wherein the gate has an adjustable threshold.

Example 14: The apparatus of example 13, wherein the output is a logichigh when the first input, the second input, and the third input arelogic high, wherein the output is a logic low when the first input, thesecond input, and the third input are logic low, wherein the outputretains its logic state when at least one of the first input, the secondinput, or the third input is a logic 1 and when the at least one of thefirst input, the second input, or the third input is a logic 0.

Example 15: The apparatus of example 13, wherein the gate comprises: afirst capacitor having a first terminal coupled to the first input, anda second terminal coupled to a summing node; a second capacitor having athird terminal coupled to the second input, and a fourth terminalcoupled to the summing node; a third capacitor having a fifth terminalcoupled to the third input, and a sixth terminal coupled to the summingnode; a fourth capacitor having a seventh terminal coupled to the fourthinput and the fifth input, and an eighth terminal coupled to the summingnode; a fifth capacitor having a ninth terminal coupled to the fourthinput and the fifth input, and a tenth terminal coupled to the summingnode; and a device coupled to the summing node and a supply rail,wherein the device is controllable by a control.

Example 16: The apparatus of example 13 comprises a circuitry to adjusta function of the gate by controlling the adjustable threshold in afirst operation mode, and wherein the circuitry is to allow the gate tooperate in accordance with the function in a second operation mode.

Example 17: A system comprising: a memory to store one or moreinstructions; a processor circuitry to execute the one or moreinstructions; and a communication device to allow the processorcircuitry to communicate with another device, wherein the processorcircuitry includes a consensus circuity which comprises an apparatusaccording to any one of examples 1 to 12 or examples 13 to 16.

Example 1a: An apparatus comprising: a first consensus circuitry todetermine a first consensus between a first input and a second input,the first consensus circuitry to generate a first output which isrepresentative of the first consensus; a second consensus circuitry todetermine a second consensus between a third input and a fourth input,the second consensus circuitry to generate a second output which isrepresentative of the second consensus; and a third consensus circuitrycoupled to the first consensus circuitry and the second consensuscircuitry, wherein the third consensus circuitry is to determine a thirdconsensus between the first output and the second output, the thirdconsensus circuitry to generate a third output which is representativeof the third consensus, wherein the first consensus circuitry, thesecond consensus circuitry, and the third consensus circuitry comprisesa first gate with a first adjustable threshold, a second gate with asecond adjustable threshold, and a third gate with a third adjustablethreshold, respectively.

Example 2a: The apparatus of example 1a comprising: a fourth consensuscircuitry to determine a fourth consensus between a fifth input and ansixth input, the fourth consensus circuitry to generate a fourth outputwhich is representative of the fourth consensus; a fifth consensuscircuitry to determine a fifth consensus between a seventh input and aneighth input, the fifth consensus circuitry to generate a fifth outputwhich is representative of the fifth consensus; and a sixth consensuscircuitry coupled to the fourth consensus circuitry and the fifthconsensus circuitry, wherein the sixth consensus circuitry is todetermine a sixth consensus between the fourth output and the fifthoutput, the sixth consensus circuitry to generate a sixth output whichis representative of the sixth consensus, wherein the fourth consensuscircuitry, the fifth consensus circuitry, and the sixth consensuscircuitry comprises a fourth gate with a fourth adjustable threshold, afifth gate with a fifth adjustable threshold, and a sixth gate with asixth adjustable threshold, respectively.

Example 3a: The apparatus of example 2a comprising seventh consensuscircuitry coupled to the third consensus circuitry and the sixthconsensus circuitry, wherein the seventh consensus circuitry is todetermine a seventh consensus between the third output and the sixthoutput, the seventh consensus circuitry to generate a seventh outputrepresentative of the seventh consensus.

Example 4a: The apparatus of example 3a, wherein the seventh consensusindicates a consensus of the first input, the second input, the thirdinput, the fourth input, the fifth input, the sixth input, the seventhinput, and the eighth input.

Example 5a: The apparatus of example 3a, wherein the seventh consensuscircuitry comprises a seventh gate with a seventh adjustable threshold.

Example 6a: The apparatus of example 1a, wherein the first gatecomprises: a first input node to receive the first input; a second inputnode to receive the second input; a third input node; a control; acircuitry to adjust logic levels of the first input, the second input,and the control in a first operation mode; and a multi-input gate toreceive the first input, the second input, and the third input, whereinand the third input node is coupled to an output of the multi-inputgate, wherein the multi-input gate comprises: a first capacitor having afirst terminal coupled to the first input node, and a second terminalcoupled to a summing node; a second capacitor having a third terminalcoupled to the second input node, and a fourth terminal coupled to thesumming node; a third capacitor having a fifth terminal coupled to thethird input node, and a sixth terminal coupled to the summing node; anda device coupled to the summing node and a supply rail, wherein thedevice is controllable by the control, wherein the circuitry is toadjust a function of the multi-input gate in the first operation mode,and wherein the circuitry is to allow the multi-input gate to operate inaccordance with the function in a second operation mode.

Example 7a: The apparatus of example 6a, wherein the function is amajority function.

Example 8a: The apparatus of example 6a, wherein the first capacitor,the second capacitor, and the third capacitor comprise linear dielectricmaterial.

Example 9a: The apparatus of example 8a, wherein the linear dielectricmaterial includes one of: SiO2, Al2O3, Li2O, HfSiO4, Sc2O3, SrO, HfO2,ZrO2, Y2O3, Ta2O5, BaO, WO3, MoO3, or TiO2.

Example 10a: The apparatus of example 6a, wherein the device is apull-up device, wherein the circuitry is to set logic levels of thefirst input, the second input, and the third input to logic high, andthe control to enable or turn on the pull-up device in the firstoperation mode to adjust a threshold of the multi-input gate to 2.

Example 11a: The apparatus of example 6a, wherein the first capacitor,the second capacitor, and the third capacitor include: a lineardielectric material includes one or more of: Si, Al, Li, Hf, Sc, Sr, Zr,Y, Ta, Ba, W, Mo, or Ti; and a top electrode and a bottom electrode,wherein the linear dielectric material is between the top electrode andthe bottom electrode, wherein the top electrode or the bottom electrodeinclude one or more of: Cu, Al, Ag, Au, W, or Co.

Example 12a: The apparatus of example 6a, wherein the first capacitor,the second capacitor, and the third capacitor include paraelectricmaterial which includes one of: SrTiO3, Ba(x)Sr(y)TiO3 (where x is −0.5,and y is 0.95), HfZrO2, Hf—Si—O, BaTiO3, La-substituted PbTiO3, leadzirconate titanate, or PMN-PT (lead magnesium niobate-lead titanate)based relaxor ferroelectrics.

Example 13a: The apparatus of example 6, wherein the first capacitor,the second capacitor, and the third capacitor include ferroelectricmaterial.

Example 14a: The apparatus of example 6a, wherein the device is a firstdevice, wherein the supply rail is a power supply rail, wherein thecontrol is a first control, wherein the multi-input gate comprises asecond device coupled to the summing node and a ground supply rail,wherein the second device is controllable by a second control.

Example 15a: The apparatus of example 14a, wherein, in the firstoperation mode, the circuitry is to adjust a threshold of themulti-input gate to 2 after the second device is enabled first, and thenthe second device is disabled, and then the first device is enabled, andthe first input is set to logic 1, the second input is set to logic 1,and the third input is set to logic 0.

Example 16a: The apparatus of example 14a, wherein, in the firstoperation mode, the circuitry is to adjust a threshold of themulti-input gate to 2 after the first device is enabled first, and thenthe first device is disabled, and then the second device is enabled, andthe first input is set to logic 1, the second input is set to logic 0,and the third input is set to logic 0.

Example 17a: The apparatus of example 14a, wherein the first capacitor,the second capacitor, and the third capacitor include ferroelectricmaterial, wherein the ferroelectric material according to theferroelectric materials discussed herein.

Example 18a: An apparatus comprising: an m-input consensus circuitrycomprising a first plurality of consensus circuitries coupled togenerate a first output indicative of a first consensus of m number ofinputs; an n-input consensus circuitry comprising a second plurality ofconsensus circuitries coupled to generate a second output indicative ofa second consensus of n number of inputs; and a 2-input consensuscircuitry coupled to the m-input consensus circuitry and the n-inputconsensus circuitry, wherein the 2-input consensus circuitry is togenerate a third output, wherein the m-input consensus circuitry, then-input consensus circuitry, and the 2-input consensus circuitrycomprise gates with adjustable threshold.

Example 19a: The apparatus of example 18a, wherein the gates withadjustable threshold are configured as majority or minority gates.

Example 20a: A system comprising: a memory to store one or moreinstructions; a processor circuitry to execute the one or moreinstructions; and a communication device to allow the processorcircuitry to communicate with another device, wherein the processorcircuitry includes a completion tree which comprises an apparatusaccording to any one of examples 1a to 17a or examples 18a to 19a.

Example 1b: An apparatus comprising: a first OR gate to generate a firstoutput which is indicative of a first OR function between a first inputand a second input; a second OR gate to generate a second output whichis indicative of a second OR function between a third input and a fourthinput; and a first consensus circuitry to determine a first consensusbetween the first output and the second output, the first consensuscircuitry to generate a first consensus output which is representativeof the first consensus, wherein the first consensus circuitry comprisesa first gate with a first adjustable threshold.

Example 2b: The apparatus of example 1b further comprising: a third ORgate to generate a third output which is indicative of a third ORfunction between a fifth input and a sixth input; a fourth OR gate togenerate a fourth output which is indicative of a fourth OR functionbetween a seventh input and an eighth input; and a second consensuscircuitry to determine a second consensus between the third output andthe fourth output, the second consensus circuitry to generate a secondconsensus output which is representative of the second consensus,wherein the second consensus circuitry comprises a second gate with asecond adjustable threshold.

Example 3b: The apparatus of example 2b further comprising a thirdconsensus circuitry coupled to the first consensus circuitry and thesecond consensus circuitry, wherein the third consensus circuitry is todetermine a third consensus between the first consensus output and thesecond consensus output, the third consensus circuitry to generate athird consensus output which is representative of the third consensus.

Example 4b: The apparatus of example 3b, wherein the third consensuscircuitry comprises a third gate with a third adjustable threshold.

Example 5b: The apparatus of example 3b, wherein the third consensusoutput indicates a valid state or a neutral state based on logic valuesof the first input, the second input, the third input, the fourth input,the fifth input, the sixth input, the seventh input, and the eighthinput.

Example 6b: The apparatus of example 1b, wherein the first OR gatecomprises a first threshold gate with a threshold which is adjusted tofunction the first threshold gate as an OR gate.

Example 7b: The apparatus of example 6b, wherein the threshold isadjusted to 1.

Example 8b: The apparatus of example 1b, wherein the first consensuscircuitry comprises: a first input node to receive the first input; asecond input node to receive the second input; a third input node; acontrol; a conditioning circuitry to adjust logic levels of the firstinput, the second input, and the control in a first operation mode; anda multi-input gate to receive the first input, the second input, and thethird input, wherein and the third input node is coupled to an output ofthe multi-input gate, wherein the multi-input gate comprises: a firstcapacitor having a first terminal coupled to the first input node, and asecond terminal coupled to a summing node; a second capacitor having athird terminal coupled to the second input node, and a fourth terminalcoupled to the summing node; a third capacitor having a fifth terminalcoupled to the third input node, and a sixth terminal coupled to thesumming node; and a device coupled to the summing node and a supplyrail, wherein the device is controllable by the control, wherein theconditioning circuitry is to adjust a function of the multi-input gatein the first operation mode, and wherein the conditioning circuitry isto allow the multi-input gate to operate in accordance with the functionin a second operation mode.

Example 9b: The apparatus of example 8b, wherein the function is amajority function.

Example 10b: The apparatus of example 8b, wherein the first capacitor,the second capacitor, and the third capacitor comprise linear dielectricmaterial, and wherein the linear dielectric material includes one of:SiO2, Al2O3, Li2O, HfSiO4, Sc2O3, SrO, HfO2, ZrO2, Y2O3, Ta2O5, BaO,WO3, MoO3, or TiO2.

Example 11b: The apparatus of example 8b, wherein the device is apull-up device, wherein the conditioning circuitry is to set logiclevels of the first input, the second input, and the third input tologic high, and the control to enable or turn on the pull-up device inthe first operation mode to adjust a threshold of the multi-input gateto 2.

Example 12b: The apparatus of example 8b, wherein the first capacitor,the second capacitor, and the third capacitor include: a lineardielectric material includes one or more of: Si, Al, Li, Hf, Sc, Sr, Zr,Y, Ta, Ba, W, Mo, or Ti; and a top electrode and a bottom electrode,wherein the linear dielectric material is between the top electrode andthe bottom electrode, wherein the top electrode or the bottom electrodeinclude one or more of: Cu, Al, Ag, Au, W, or Co.

Example 13b: The apparatus of example 8b, wherein the first capacitor,the second capacitor, and the third capacitor include paraelectricmaterial which includes one of: SrTiO3, Ba(x)Sr(y)TiO3 (where x is −0.5,and y is 0.95), HfZrO2, Hf—Si—O, BaTiO3, La-substituted PbTiO3, leadzirconate titanate, or PMN-PT (lead magnesium niobate-lead titanate)based relaxor ferroelectrics.

Example 14b: The apparatus of example 8b, wherein the first capacitor,the second capacitor, and the third capacitor include ferroelectricmaterial.

Example 15b: The apparatus of example 8b, wherein the device is a firstdevice, wherein the supply rail is a power supply rail, wherein thecontrol is a first control, wherein the multi-input gate comprises asecond device coupled to the summing node and a ground supply rail,wherein the second device is controllable by a second control.

Example 16b: The apparatus of example 15b, wherein, in the firstoperation mode, the conditioning circuitry is to adjust a threshold ofthe multi-input gate to 2 after the second device is enabled first, andthen the second device is disabled, and then the first device isenabled, and the first input is set to logic 1, the second input is setto logic 1, and the third input is set to logic 0.

Example 17b: The apparatus of example 16b, wherein, in the firstoperation mode, the conditioning circuitry is to adjust a threshold ofthe multi-input gate to 2 after the first device is enabled first, andthen the first device is disabled, and then the second device isenabled, and the first input is set to logic 1, the second input is setto logic 0, and the third input is set to logic 0.

Example 18b: An apparatus comprising: an m-input validity circuitry togenerate a first output indicative of a first validity of m number ofinputs; an n-input validity circuitry to generate a second outputindicative of a second validity of n number of inputs; and a 2-inputconsensus circuitry coupled to the m-input validity circuitry and then-input validity circuitry, wherein the 2-input consensus circuitry isto generate a third output, wherein the m-input validity circuitry, then-input validity circuitry, and the 2-input consensus circuitry comprisegates with adjustable threshold.

Example 19b: The apparatus of example 18b, wherein the gates with theadjustable threshold are configured as majority, minority gates, or ORgates.

Example 20b: A system comprising: a memory to store one or moreinstructions; a processor circuitry to execute the one or moreinstructions; and a communication device to allow the processorcircuitry to communicate with another device, wherein the processorcircuitry includes a validity tree which comprises an apparatusaccording to any one of examples 1b to 17b, or examples 18b to 19b.

Example 1c: An apparatus comprising: a first input; a second input; anda consensus circuitry coupled to the first input and the second input,wherein the consensus circuitry is to generate a consensus output whichis indicative of a consensus of the first input and the second input,wherein the consensus circuitry comprises a gate to receive the firstinput, the second input, and a third input, wherein and the third inputis coupled to an output of the gate which is the consensus output,wherein the gate comprises: a first capacitor having a first terminalcoupled to the first input, and a second terminal coupled to a summingnode; a second capacitor having a third terminal coupled to the secondinput, and a fourth terminal coupled to the summing node; and a thirdcapacitor having a fifth terminal coupled to the third input, and asixth terminal coupled to the summing node, wherein the first capacitor,the second capacitor, and the third capacitor are planar stackedcapacitors.

Example 2c: The apparatus of example 1c comprising a circuitry to adjustlogic levels of the first input, the second input, and a control in afirst operation mode.

Example 3c: The apparatus of example 2c, wherein the gate comprises adevice coupled to the summing node and a supply rail, wherein the deviceis controllable by the control, wherein the circuitry is to adjust afunction of the gate in the first operation mode, and wherein thecircuitry is to allow the gate to operate in accordance with thefunction in a second operation mode.

Example 4c: The apparatus of example 3c, wherein the function is amajority function.

Example 5c: The apparatus of example 1c, wherein the first capacitor,the second capacitor, and the third capacitor comprise linear dielectricmaterial or paraelectric material.

Example 6c: The apparatus of example 1c, wherein the gate comprises: afirst metal layer extending along an x-plane; a second metal layerextending along the x-plane, wherein the second metal layer is above thefirst metal layer; a first via extending along a y-plane, wherein they-plane is orthogonal to the x-plane, wherein the first via couples thefirst metal layer with the second metal layer; a second via extendingalong the y-plane, wherein the second via couples the second metallayer, wherein the second via is above the first via; a first pedestalon the first metal layer, wherein the first pedestal is laterally offsetfrom the first via; a second pedestal on the second metal layer, whereinthe second pedestal is laterally offset from the second via, wherein thesumming node is coupled to the first via; a first input line extendingalong a z-plane, wherein the z-plane is orthogonal to the x-plane andthe y-plane, wherein the first input is coupled to the first input line;and a second input line extending along the z-plane, wherein the secondinput is coupled to the second input line.

Example 7c: The apparatus of example 6c, wherein the first capacitorcomprises a first planar stack of materials including a first lineardielectric material or a first paraelectric material, wherein the firstplanar stack of materials has a first top electrode and a first bottomelectrode, wherein the first linear dielectric material or the firstparaelectric material is between the first top electrode and the firstbottom electrode, wherein the first bottom electrode is on the firstpedestal, wherein the first input line is on the first top electrode.

Example 8c: The apparatus of example 7c, wherein the second capacitorcomprises a second planar stack of materials including a second lineardielectric material or a second paraelectric material, wherein thesecond planar stack of materials has a second top electrode and a secondbottom electrode, wherein the second linear dielectric material or thesecond paraelectric material is between the second top electrode of thesecond planar stack of materials and the second bottom electrode and thesecond planar stack of materials, wherein the second bottom electrode ison the second pedestal, wherein the second input line is on the secondtop electrode of the second planar stack of materials.

Example 9c: The apparatus of example 7c, wherein the first lineardielectric material includes one of: SiO2, Al2O3, Li2O, HfSiO4, Sc2O3,SrO, HfO2, ZrO2, Y2O3, Ta2O5, BaO, WO3, MoO3, or TiO2.

Example 10c: The apparatus of example 3c, wherein the device is apull-up device coupled to the summing node and a power supply rail.

Example 11c: The apparatus of example 10c, wherein the circuitry is toset logic levels of the first input, the second input, and the thirdinput to logic high, and the control to enable or turn on the pull-updevice in the first operation mode to adjust a threshold of the gate to2.

Example 12c: The apparatus of example 10c, wherein the pull-up device iscontrolled by the control, wherein voltages on the first input, thesecond input, and the control are set in the first operation mode toadjust a threshold of the apparatus, wherein the control is to cause thepull-up device to be off in the second operation mode, wherein thesecond operation mode occurs after the first operation mode.

Example 13c: The apparatus of example 1c, wherein the first capacitor,the second capacitor, or the third capacitor include: a lineardielectric material includes one or more of: Si, Al, Li, Hf, Sc, Sr, Zr,Y, Ta, Ba, W, Mo, or Ti; and a top electrode and a bottom electrode,wherein the linear dielectric material is between the top electrode andthe bottom electrode, wherein the top electrode or the bottom electrodeinclude one or more of: Cu, Al, Ag, Au, W, or Co.

Example 14c: The apparatus of example 1c, wherein the first capacitor,the second capacitor, or the third capacitor include paraelectricmaterial which includes one of: SrTiO3, Ba(x)Sr(y)TiO3 (where x is −0.5,and y is 0.95), HfZrO2, Hf—Si—O, BaTiO3, La-substituted PbTiO3, leadzirconate titanate, or PMN-PT (lead magnesium niobate-lead titanate)based relaxor ferroelectrics.

Example 15c: An apparatus comprising: a first input; a second input; athird input; a fourth input; a fifth input; and a gate to provide anoutput which is a consensus of the first input, the second input, andthe third input, wherein the output is coupled to the fourth input andthe fifth input, wherein the gate has a plurality of capacitors that areplanar capacitors, and wherein the planar capacitors are verticallystacked.

Example 16c: The apparatus of example 15c, wherein the output is a logichigh when the first input, the second input, and the third input arelogic high, wherein the output is a logic low when the first input, thesecond input, and the third input are logic low, wherein the outputretains its logic state when at least one of the first input, the secondinput, or the third input is a logic 1 and when the at least one of thefirst input, the second input, or the third input is a logic 0.

Example 17c: The apparatus of example 15c, wherein the gate comprises: afirst capacitor having a first terminal coupled to the first input, anda second terminal coupled to a summing node; a second capacitor having athird terminal coupled to the second input, and a fourth terminalcoupled to the summing node; a third capacitor having a fifth terminalcoupled to the third input, and a sixth terminal coupled to the summingnode; a fourth capacitor having a seventh terminal coupled to the fourthinput and the fifth input, and an eighth terminal coupled to the summingnode; a fifth capacitor having a ninth terminal coupled to the fourthinput and the fifth input, and a tenth terminal coupled to the summingnode, wherein the first capacitor, the second capacitor, the thirdcapacitor, the fourth capacitor, and the fifth capacitor are part of theplurality of capacitors; and a device coupled to the summing node and asupply rail, wherein the device is controllable by a control.

Example 18c: The apparatus of example 15c comprises a circuitry toadjust a function of the gate by controlling the adjustable threshold ina first operation mode, and wherein the circuitry is to allow the gateto operate in accordance with the function in a second operation mode.

Example 19c: A system comprising: a memory to store one or moreinstructions; a processor circuitry to execute the one or moreinstructions; and a communication device to allow the processorcircuitry to communicate with another device, wherein the processorcircuitry includes a consensus circuity which comprises an apparatusaccording to any one of examples 1c to 14c, or examples 15c to 18c.

Example 1d: An apparatus comprising: a first input; a second input; anda consensus circuitry coupled to the first input and the second input,wherein the consensus circuitry is to generate a consensus output whichis indicative of a consensus of the first input and the second input,wherein the consensus circuitry comprises a gate to receive the firstinput, the second input, and a third input, wherein and the third inputis coupled to an output of the gate which is the consensus output,wherein the gate comprises: a first capacitor having a first terminalcoupled to the first input, and a second terminal coupled to a summingnode; a second capacitor having a third terminal coupled to the secondinput, and a fourth terminal coupled to the summing node; and a thirdcapacitor having a fifth terminal coupled to the third input, and asixth terminal coupled to the summing node, wherein the first capacitor,the second capacitor, and the third capacitor are non-planar stackedcapacitors.

Example 2d: The apparatus of example 1d comprising a circuitry to adjustlogic levels of the first input, the second input, and a control in afirst operation mode.

Example 3d: The apparatus of example 2d, wherein the gate comprises adevice coupled to the summing node and a supply rail, wherein the deviceis controllable by the control, wherein the circuitry is to adjust afunction of the gate in the first operation mode, and wherein thecircuitry is to allow the gate to operate in accordance with thefunction in a second operation mode.

Example 4d: The apparatus of example 3d, wherein the function is amajority function.

Example 5d: The apparatus of example 1d, wherein the first capacitor,the second capacitor, and the third capacitor comprise linear dielectricmaterial or paraelectric material.

Example 6d: The apparatus of example 1d, wherein the gate comprises avia extending along a y-plane, wherein the y-plane is orthogonal to anx-plane, wherein the via couples to a first metal layer; a first inputline extending along the x-plane or a z-plane, wherein the z-plane isorthogonal to the x-plane and the y-plane, wherein the first input lineis on an outer portion of the first capacitor, wherein the first inputline is coupled to the first input; a second input line extending alongthe x-plane or the z-plane, wherein the second input line is on anoutput portion of the second capacitor, wherein the second input line iscoupled to the second input; and a first transistor coupled to the viaand a supply rail, wherein: the first capacitor includes a first lineardielectric material or a first paraelectric material, wherein the firstcapacitor includes an electrode coupled to the via, wherein theelectrode is in a middle of the first capacitor; the second capacitorincludes a second linear dielectric material or a second paraelectricmaterial, wherein the electrode passes through a middle of the secondcapacitor; and the third capacitor including a third linear dielectricmaterial or a third paraelectric material, wherein the electrode passesthrough a middle of the third capacitor.

Example 7d: The apparatus of example 6d, wherein the first capacitorincludes: a first layer coupled to the electrode, wherein the firstlayer comprises metal; a second layer comprising the first lineardielectric material, wherein the second layer is around the first layer;and a third layer around the second layer, wherein the third layercomprises metal, wherein the second input line is adjacent to part ofthe third layer.

Example 8d: The apparatus of example 7d, wherein: the first layer has afirst circumference; the second layer has a second circumference; andthe third layer has a third circumference, wherein the thirdcircumference is larger than the second circumference, wherein thesecond circumference is larger than the first circumference.

Example 9d: The apparatus of example 6d, wherein the first lineardielectric material includes one of: SiO2, Al2O3, Li2O, HfSiO4, Sc2O3,SrO, HfO2, ZrO2, Y2O3, Ta2O5, BaO, WO3, MoO3, or TiO2.

Example 10d: The apparatus of example 3d, wherein the device is apull-up device coupled to the summing node and a power supply rail.

Example 11d: The apparatus of example 10d, wherein the circuitry is toset logic levels of the first input, the second input, and the thirdinput to logic high, and the control to enable or turn on the pull-updevice in the first operation mode to adjust a threshold of the gate to2.

Example 12d: The apparatus of example 10d, wherein the pull-up device iscontrolled by the control, wherein voltages on the first input, thesecond input, and the control are set in the first operation mode toadjust a threshold of the apparatus, wherein the control is to cause thepull-up device to be off in the second operation mode, wherein thesecond operation mode occurs after the first operation mode.

Example 13d: The apparatus of example 1d, wherein the first capacitor,the second capacitor, or the third capacitor include: a lineardielectric material includes one or more of: Si, Al, Li, Hf, Sc, Sr, Zr,Y, Ta, Ba, W, Mo, or Ti; and a top electrode and a bottom electrode,wherein the linear dielectric material is between the top electrode andthe bottom electrode, wherein the top electrode or the bottom electrodeinclude one or more of: Cu, Al, Ag, Au, W, or Co.

Example 14d: The apparatus of example 1d, wherein the first capacitor,the second capacitor, or the third capacitor include paraelectricmaterial which includes one of: SrTiO3, Ba(x)Sr(y)TiO3 (where x is −0.5,and y is 0.95), HfZrO2, Hf—Si—O, BaTiO3, La-substituted PbTiO3, leadzirconate titanate, or PMN-PT (lead magnesium niobate-lead titanate)based relaxor ferroelectrics.

Example 15d: An apparatus comprising: a first input; a second input; athird input; a fourth input; a fifth input; and a gate to provide anoutput which is a consensus of the first input, the second input, andthe third input, wherein the output is coupled to the fourth input andthe fifth input, wherein the gate has a plurality of capacitors that arenon-planar capacitors, wherein the non-planar capacitors are verticallystacked.

Example 16d: The apparatus of example 15d, wherein the output is a logichigh when the first input, the second input, and the third input arelogic high, wherein the output is a logic low when the first input, thesecond input, and the third input are logic low, wherein the outputretains its logic state when at least one of the first input, the secondinput, or the third input is a logic 1 and when the at least one of thefirst input, the second input, or the third input is a logic 0.

Example 17d: The apparatus of example 15d, wherein the gate comprises: afirst transistor, the first transistor having a source region and adrain region, and a gate, wherein the first transistor is controllableby a first control; a first via coupled to the source region; a secondvia coupled to the drain region; a first metal layer over the first via,the first metal layer extending along an x-plane; a third via over thefirst metal layer, the third via in direct connection to the first metallayer, wherein the third via extends along a y-plane, wherein they-plane is orthogonal to an x-plane; a first non-planar stack ofmaterials including a first linear dielectric material or a firstparaelectric material, wherein the first non-planar stack of materialsincludes an electrode coupled to the third via, wherein the electrode isin a middle of the first non-planar stack of materials; a secondnon-planar stack of materials including a second linear dielectricmaterial or a second paraelectric material, wherein the electrode passesthrough a middle of the second non-planar stack of materials; a firstinput line extending along the x-plane or a z-plane, wherein the z-planeis orthogonal to the x-plane and the y-plane, wherein the first inputline is on a portion of the first non-planar stack of materials, whereinthe first input is coupled to the first input line; and a second inputline extending along the x-plane or the z-plane, wherein the secondinput line is on a portion of the second non-planar stack of materials,wherein the second input is coupled to the second input line.

Example 18d: The apparatus of example 15d comprises a circuitry toadjust a function of the gate by controlling the adjustable threshold ina first operation mode, and wherein the circuitry is to allow the gateto operate in accordance with the function in a second operation mode.

Example 19d: A system comprising: a memory to store one or moreinstructions; a processor circuitry to execute the one or moreinstructions; and a communication device to allow the processorcircuitry to communicate with another device, wherein the processorcircuitry includes a consensus circuity which comprises an apparatusaccording to any one of examples 1d to 14d, or examples 15d to 18d.

Example 1e: An apparatus comprising: a first input; a second input; anda consensus circuitry coupled to the first input and the second input,wherein the consensus circuitry is to generate a consensus output whichis indicative of a consensus of the first input and the second input,wherein the consensus circuitry comprises a gate to receive the firstinput, the second input, and a third input, wherein and the third inputis coupled to an output of the gate which is the consensus output,wherein the gate comprises: a first capacitor having a first terminalcoupled to the first input, and a second terminal coupled to a summingnode, wherein the first capacitor includes a first ferroelectricmaterial; a second capacitor having a third terminal coupled to thesecond input, and a fourth terminal coupled to the summing node, whereinthe second capacitor includes a second ferroelectric material; and athird capacitor having a fifth terminal coupled to the third input, anda sixth terminal coupled to the summing node, wherein the thirdcapacitor includes a third ferroelectric material, wherein the firstcapacitor, the second capacitor, and the third capacitor are planarstacked capacitors.

Example 2e: The apparatus of example 1e comprising a circuitry to adjustlogic levels of the first input, the second input, and a control in afirst operation mode.

Example 3e: The apparatus of example 2e, wherein the gate comprises: apull-up device coupled to the summing node and a supply rail, whereinthe pull-up device is controllable by a first control, wherein thecircuitry is to adjust a function of the gate in the first operationmode, and wherein the circuitry is to allow the gate to operate inaccordance with the function in a second operation mode; and a pull-downdevice coupled to the summing node and a ground.

Example 4e: The apparatus of example 3e, wherein the function is amajority function.

Example 5e: The apparatus of example 1e, wherein the gate comprises: afirst metal layer extending along an x-plane; a second metal layerextending along the x-plane, wherein the second metal layer is above thefirst metal layer; a first via extending along a y-plane, wherein they-plane is orthogonal to the x-plane, wherein the first via couples thefirst metal layer with the second metal layer; a second via extendingalong the y-plane, wherein the second via couples the second metallayer, wherein the second via is above the first via; a first pedestalon the first metal layer, wherein the first pedestal is laterally offsetfrom the first via; a second pedestal on the second metal layer, whereinthe second pedestal is laterally offset from the second via; a summingnode coupled to the first via; a first input line extending along az-plane, wherein the z-plane is orthogonal to the x-plane and they-plane, wherein the first input line is coupled to the first input; anda second input line extending along the z-plane, wherein the secondinput line is coupled to the second input.

Example 6e: The apparatus of example 5e, wherein the first capacitorcomprises a first planar stack of materials including the firstferroelectric material, wherein the first planar stack of materials hasa first top electrode and a first bottom electrode, wherein the firstferroelectric material is between the first top electrode and the firstbottom electrode, wherein the first bottom electrode is on the firstpedestal, wherein the first input line is on the first top electrode.

Example 7e: The apparatus of example 6e, wherein the second capacitorcomprises a second planar stack of materials including the secondferroelectric material, wherein the second planar stack of materials hasa second top electrode and a second bottom electrode, wherein the secondferroelectric material is between the second top electrode of the secondplanar stack of materials and the second bottom electrode and the secondplanar stack of materials, wherein the second bottom electrode is on thesecond pedestal, wherein the second input line is on the second topelectrode of the second planar stack of materials.

Example 8e: The apparatus of example 7e, wherein the first ferroelectricmaterial or the second ferroelectric material includes any of theferroelectric materials discussed herein.

Example 9e: The apparatus of example 6e, wherein the first top electrodeand the first bottom electrode of the first planar stack of materialsincludes one or more of: Cu, Al, Ag, Au, W, or Co.

Example 10e: The apparatus of example 3e, wherein the pull-up device iscontrolled by a first control, wherein the pull-down device iscontrolled by a second control, wherein voltages of the first input, thesecond input, the first control, and the second control are set in afirst operation mode to adjust a threshold of the apparatus, wherein thefirst control is to cause the pull-up device to be off in a secondoperation mode, wherein the second control is to wherein the secondoperation mode occurs after the first operation mode.

Example 11e: An apparatus comprising: a first input; a second input; athird input; a fourth input; a fifth input; and a gate to provide anoutput which is a consensus of the first input, the second input, andthe third input, wherein the output is coupled to the fourth input andthe fifth input, wherein the gate has a plurality of capacitors that areplanar capacitors having ferroelectric material, wherein the planarcapacitors are vertically stacked.

Example 12e: The apparatus of example 11e, wherein the output is a logichigh when the first input, the second input, and the third input arelogic high, wherein the output is a logic low when the first input, thesecond input, and the third input are logic low, wherein the outputretains its logic state when at least one of the first input, the secondinput, or the third input is a logic 1 and when the at least one of thefirst input, the second input, or the third input is a logic 0.

Example 13e: The apparatus of example 11e, wherein the gate comprises: afirst transistor, the first transistor having a first source region anda first drain region, and a first gate, wherein the first gate iscontrollable by a first control; a second transistor, the secondtransistor having a second source region and a second drain region, anda second gate, wherein the second gate is controllable by a secondcontrol; a first via is coupled to the first source region; a second viais coupled to the first drain region; a first metal layer over the firstvia, the first metal layer extending along an x-plane; a second etchstop layer over the first metal layer; a third via, over the first metallayer, and etched through the second etch stop layer, the third via indirect connection to the first metal layer; a second metal layerextending along the x-plane, wherein the second metal layer is above thefirst metal layer, wherein the second metal layer couples the third via;an interlayer dielectric between the first metal layer and the secondmetal layer; a first pedestal filled with metal, wherein the firstpedestal is coupled to the second metal layer; a first plurality oflayers to form a first planar capacitor, wherein the first plurality oflayers includes a first ferroelectric dielectric material, wherein afirst layer of the first plurality of layers is in contact with a topportion of the first pedestal, wherein a second layer of the firstplurality of layers is coupled to a first input line, wherein the firstinput line is coupled to the first input; a fourth via in directconnection to the second metal layer; a third metal layer over thefourth via, wherein the first plurality of layers is between the secondmetal layer and the third metal layer; a second pedestal filled withmetal, wherein the second pedestal is coupled to the third metal layer;and a second plurality of layers to form a second planar capacitor,wherein the second plurality of layers includes a second ferroelectricdielectric material, wherein a first layer of the second plurality oflayers is in direct contact with a top portion of the second pedestal,wherein a second layer of the second plurality of layers is coupled to asecond input line, wherein the second input line is coupled to thesecond input.

Example 14e: The apparatus of example 11e, wherein the gate comprises: afirst capacitor having a first terminal coupled to the first input, anda second terminal coupled to a summing node; a second capacitor having athird terminal coupled to the second input, and a fourth terminalcoupled to the summing node; a third capacitor having a fifth terminalcoupled to the third input, and a sixth terminal coupled to the summingnode; a fourth capacitor having a seventh terminal coupled to the fourthinput and the fifth input, and an eighth terminal coupled to the summingnode; a fifth capacitor having a ninth terminal coupled to the fourthinput and the fifth input, and a tenth terminal coupled to the summingnode, wherein the first capacitor, the second capacitor, the thirdcapacitor, the fourth capacitor, and the fifth capacitor are part of theplurality of capacitors; a pull-up device coupled to the summing nodeand a supply rail, wherein the pull-up device is controllable by a firstcontrol; and a pull-down device coupled to the summing node a groundrail, wherein the pull-down device is controllable by a second control.

Example 15e: The apparatus of example 11e comprises a circuitry toadjust a function of the gate by controlling the adjustable threshold ina first operation mode, and wherein the circuitry is to allow the gateto operate in accordance with the function in a second operation mode.

Example 16e: A system comprising: a memory to store one or moreinstructions; a processor circuitry to execute the one or moreinstructions; and a communication device to allow the processorcircuitry to communicate with another device, wherein the processorcircuitry includes a consensus circuity which comprises an apparatusaccording to any one of examples 1e to 10e, or examples 11e to 15e.

Example 1f: An apparatus comprising: a first input; a second input; anda consensus circuitry coupled to the first input and the second input,wherein the consensus circuitry is to generate a consensus output whichis indicative of a consensus of the first input and the second input,wherein the consensus circuitry comprises a gate to receive the firstinput, the second input, and a third input, wherein and the third inputis coupled to an output of the gate which is the consensus output,wherein the gate comprises: a first capacitor having a first terminalcoupled to the first input, and a second terminal coupled to a summingnode, wherein the first capacitor includes a first ferroelectricmaterial; a second capacitor having a third terminal coupled to thesecond input, and a fourth terminal coupled to the summing node, whereinthe second capacitor includes a second ferroelectric material; and athird capacitor having a fifth terminal coupled to the third input, anda sixth terminal coupled to the summing node, wherein the thirdcapacitor includes a third ferroelectric material, wherein the firstcapacitor, the second capacitor, and the third capacitor are non-planarstacked capacitors.

Example 2f: The apparatus of example if comprising a circuitry to adjustlogic levels of the first input, the second input, and a control in afirst operation mode.

Example 3f: The apparatus of example 2f, wherein the gate comprises: apull-up device coupled to the summing node and a supply rail, whereinthe pull-up device is controllable by a first control, wherein thecircuitry is to adjust a function of the gate in the first operationmode, and wherein the circuitry is to allow the gate to operate inaccordance with the function in a second operation mode; and a pull-downdevice coupled to the summing node and a ground.

Example 4f: The apparatus of example 3f, wherein the function is amajority function.

Example 5f: The apparatus of example 1f, wherein the gate comprises: avia extending along a y-plane, wherein the y-plane is orthogonal to anx-plane, wherein the via couples to a first metal layer; a first inputline extending along the x-plane or a z-plane, wherein the z-plane isorthogonal to the x-plane and the y-plane, wherein the first input lineis on an outer portion of the first capacitor; a second input lineextending along the x-plane or the z-plane, wherein the second inputline is on an output portion of the second capacitor; a first transistorcoupled to the via and a supply rail; and a second transistor coupled tothe via and a ground, wherein: the first capacitor includes an electrodecoupled to the via, wherein the electrode is in a middle of the firstcapacitor; the electrode passes through a middle of the secondcapacitor; and the electrode passes through a middle of the thirdcapacitor.

Example 6f: The apparatus of example 5f, wherein the first transistor iscontrolled by a first control, wherein the second transistor iscontrolled by a second control, wherein voltages on the first inputline, the second input line, the first control, and the second controlare set in a first operation mode to adjust a threshold of theapparatus.

Example 7f: The apparatus of example 6f, wherein the first control is tocause the first transistor to be off in a second operation mode, whereinthe second control is to cause the second transistor to be off in thesecond operation mode, wherein the second operation mode occurs afterthe first operation mode.

Example 8f: The apparatus of example 5f, wherein the first capacitorincludes: a first layer coupled to the electrode, wherein the firstlayer comprises metal; a second layer around the first layer, whereinthe second layer comprises a first conductive oxide; a third layercomprising the first ferroelectric material, wherein the third layer isaround the second layer; a fourth layer around the third layer, whereinthe fourth layer comprises a second conductive oxide, wherein the fourthlayer is around the third layer; and a fifth layer around the fourthlayer, wherein the fifth layer comprises metal, wherein the first inputline is adjacent to part of the fifth layer.

Example 9f: The apparatus of example 8f, wherein: the first layer has afirst circumference; the second layer has a second circumference; thethird layer has a third circumference; the fourth layer has a fourthcircumference; and the fifth layer has a fifth circumference, whereinthe fifth circumference is larger than the fourth circumference, whereinthe fourth circumference is larger than the third circumference, whereinthe third circumference is larger than the second circumference, whereinthe second circumference is larger than the first circumference.

Example 10f: The apparatus of example 1f, wherein the firstferroelectric material or the second ferroelectric material includes anyone of the ferroelectric materials discussed herein.

Example 11f: The apparatus of example 6f, wherein the electrode includesone or more of: Cu, Al, Ag, Au, W, or Co.

Example 12f: The apparatus of example 3f, wherein the pull-up device iscontrolled by a first control, wherein the pull-down device iscontrolled by a second control, wherein voltages of the first input, thesecond input, the first control, and the second control are set in afirst operation mode to adjust a threshold of the apparatus, wherein thefirst control is to cause the pull-up device to be off in a secondoperation mode, wherein the second control is to wherein the secondoperation mode occurs after the first operation mode.

Example 13f: An apparatus comprising: a first input; a second input; athird input; a fourth input; a fifth input; and a gate to provide anoutput which is a consensus of the first input, the second input, andthe third input, wherein the output is coupled to the fourth input andthe fifth input, wherein the gate has a plurality of capacitors that arenon-planar capacitors having ferroelectric material, wherein thenon-planar capacitors are vertically stacked.

Example 14f: The apparatus of example 13f, wherein the output is a logichigh when the first input, the second input, and the third input arelogic high, wherein the output is a logic low when the first input, thesecond input, and the third input are logic low, wherein the outputretains its logic state when at least one of the first input, the secondinput, or the third input is a logic 1 and when the at least one of thefirst input, the second input, or the third input is a logic 0.

Example 15f: The apparatus of example 13f, wherein the gate comprises: afirst transistor, the first transistor having a source region and adrain region, and a gate, wherein the first transistor is controllableby a first control; a first via coupled to the source region; a secondvia coupled to the drain region; a first metal layer over the first via,the first metal layer extending along an x-plane; a third via over thefirst metal layer, the third via in direct connection to the first metallayer, wherein the third via extends along a y-plane, wherein they-plane is orthogonal to an x-plane; a first non-planar stack ofmaterials including a first ferroelectric material, wherein the firstnon-planar stack of materials includes an electrode coupled to the thirdvia, wherein the electrode is in a middle of the first non-planar stackof materials; a second non-planar stack of materials including a secondferroelectric material, wherein the electrode passes through a middle ofthe second non-planar stack of materials; a first input line extendingalong the x-plane or a z-plane, wherein the z-plane is orthogonal to thex-plane and the y-plane, wherein the first input line is on a portion ofthe first non-planar stack of materials, wherein the first input iscoupled to the first input line; and a second input line extending alongthe x-plane or the z-plane, wherein the second input line is on aportion of the second non-planar stack of materials, wherein the secondinput is coupled to the second input line.

Example 16f: The apparatus of example 13f comprises a circuitry toadjust a function of the gate by controlling the adjustable threshold ina first operation mode, and wherein the circuitry is to allow the gateto operate in accordance with the function in a second operation mode.

Example 17f: A system comprising: a memory to store one or moreinstructions; a processor circuitry to execute the one or moreinstructions; and a communication device to allow the processorcircuitry to communicate with another device, wherein the processorcircuitry includes a consensus circuity which comprises an apparatusaccording to any of the examples 1f to 12f, and examples 13f to 16f.

Example 1g: An apparatus comprising: a first input; a second input; athird input; and a gate to receive the first input, the second input,and the third input, wherein and the third input is coupled to an outputof the gate, wherein the output is a consensus of the first input andthe second input, wherein the gate comprises: a first capacitor having afirst terminal connected to the first input, and a second terminalcoupled to a summing node, wherein the first capacitor comprises a firstnonlinear polar material; a second capacitor having a third terminalconnected to the second input, and a fourth terminal coupled to thesumming node, wherein the first capacitor comprises a second nonlinearpolar material; a third capacitor having a fifth terminal connected tothe third input, and a sixth terminal coupled to the summing node,wherein the third capacitor comprises a third nonlinear polar material;and a device connected to the summing node and a supply rail, whereinthe device has a gate terminal controllable by a control separate fromthe summing node.

Example 2g: The apparatus of example 1g, wherein first capacitor, thesecond capacitor, and the third capacitor are configured such that avoltage on the summing node is to reduce static leakage through thedevice.

Example 3g: The apparatus of example 2g, wherein the voltage on thesumming node is close to rail-to-rail.

Example 4g: The apparatus of example 1g, wherein the first nonlinearpolar material includes paraelectric material which includes one of:SrTiO3, Ba(x)Sr(y)TiO3 (where x is −0.5, and y is 0.95), HfZrO2,Hf—Si—O, BaTiO3, La-substituted PbTiO3, lead zirconate titanate, orPMN-PT (lead magnesium niobate-lead titanate) based relaxorferroelectrics.

Example 5g: The apparatus of example 1g, wherein the first nonlinearpolar material comprises a first ferroelectric material which includesany of the ferroelectric materials discussed herein.

Example 6g: The apparatus of example 1g, wherein the gate is to performa majority or a minority function of the first input, the second input,and the third input.

Example 7g: The apparatus of example 1g, wherein the device is turned onin a reset mode, and wherein the device turned off in an evaluation modeseparate from the reset mode.

Example 8g: An apparatus comprising: a first input; a second input; athird input; a fourth input; a fifth input; and a gate to provide anoutput which is a consensus of the first input, the second input, andthe third input, wherein the output is coupled to the fourth input andthe fifth input, wherein the gate includes a plurality of capacitorsthat are coupled to the first input, the second input, the third input,the fourth input, and the fifth input, and wherein the plurality ofcapacitors comprises nonlinear polar material, wherein the gate includesa device connected to the gate and controllable by a controldisconnected from the plurality of capacitors.

Example 9g: The apparatus of example 8g, wherein the plurality ofcapacitors is configured such that a voltage on a summing node is toreduce static leakage through the device, wherein the plurality ofcapacitors is connected to the summing node.

Example 10g: The apparatus of example 9g, wherein the voltage on thesumming node is close to rail-to-rail.

Example 11g: The apparatus of example 8g, wherein the nonlinear polarmaterial includes paraelectric material which includes one of: SrTiO3,Ba(x)Sr(y)TiO3 (where x is −0.5, and y is 0.95), HfZrO2, Hf—Si—O,BaTiO3, La-substituted PbTiO3, lead zirconate titanate, or PMN-PT (leadmagnesium niobate-lead titanate) based relaxor ferroelectrics.

Example 12g: The apparatus of example 8g, wherein the nonlinear polarmaterial includes ferroelectric material.

Example 13g: The apparatus of example 8g, wherein the gate is to performa majority or a minority function of the first input, the second input,the third input, the fourth input, and the fifth input.

Example 14g: The apparatus of example 8g, wherein the device is turnedon in a reset mode, and wherein the device turned off in an evaluationmode separate from the reset mode.

Example 15g: A system comprising: a memory to store one or moreinstructions; a processor circuitry to execute the one or moreinstructions; and a communication device to allow the processorcircuitry to communicate with another device, wherein the processorcircuitry includes a consensus circuity which comprises an apparatusaccording to any one of the examples 1g to 7g, or examples 8g to 14g.

An abstract is provided that will allow the reader to ascertain thenature and gist of the technical disclosure. The abstract is submittedwith the understanding that it will not be used to limit the scope ormeaning of the claims. The following claims are hereby incorporated intothe detailed description, with each claim standing on its own as aseparate embodiment.

We claim:
 1. An apparatus comprising: a first input; a second input; anda consensus circuitry coupled to the first input and the second input,wherein the consensus circuitry is to generate a consensus output whichis indicative of a consensus of the first input and the second input,wherein the consensus circuitry comprises a gate to receive the firstinput, the second input, and a third input, wherein and the third inputis coupled to an output of the gate which is the consensus output,wherein the gate comprises: a first capacitor having a first terminalcoupled to the first input, and a second terminal coupled to a summingnode; a second capacitor having a third terminal coupled to the secondinput, and a fourth terminal coupled to the summing node; and a thirdcapacitor having a fifth terminal coupled to the third input, and asixth terminal coupled to the summing node, wherein the first capacitor,the second capacitor, and the third capacitor are planar stackedcapacitors.
 2. The apparatus of claim 1 comprising a circuitry to adjustlogic levels of the first input, the second input, and a control in afirst operation mode.
 3. The apparatus of claim 2, wherein the gatecomprises a device coupled to the summing node and a supply rail,wherein the device is controllable by the control, wherein the circuitryis to adjust a function of the gate in the first operation mode, andwherein the circuitry is to allow the gate to operate in accordance withthe function in a second operation mode.
 4. The apparatus of claim 3,wherein the function is a majority function.
 5. The apparatus of claim1, wherein the first capacitor, the second capacitor, and the thirdcapacitor comprise linear dielectric material or paraelectric material.6. The apparatus of claim 1, wherein the gate comprises: a first metallayer extending along an x-plane; a second metal layer extending alongthe x-plane, wherein the second metal layer is above the first metallayer; a first via extending along a y-plane, wherein the y-plane isorthogonal to the x-plane, wherein the first via couples the first metallayer with the second metal layer; a second via extending along they-plane, wherein the second via couples the second metal layer, whereinthe second via is above the first via; a first pedestal on the firstmetal layer, wherein the first pedestal is laterally offset from thefirst via; a second pedestal on the second metal layer, wherein thesecond pedestal is laterally offset from the second via, wherein thesumming node is coupled to the first via; a first input line extendingalong a z-plane, wherein the z-plane is orthogonal to the x-plane andthe y-plane, wherein the first input is coupled to the first input line;and a second input line extending along the z-plane, wherein the secondinput is coupled to the second input line.
 7. The apparatus of claim 6,wherein the first capacitor comprises a first planar stack of materialsincluding a first linear dielectric material or a first paraelectricmaterial, wherein the first planar stack of materials has a first topelectrode and a first bottom electrode, wherein the first lineardielectric material or the first paraelectric material is between thefirst top electrode and the first bottom electrode, wherein the firstbottom electrode is on the first pedestal, wherein the first input lineis on the first top electrode.
 8. The apparatus of claim 7, wherein thesecond capacitor comprises a second planar stack of materials includinga second linear dielectric material or a second paraelectric material,wherein the second planar stack of materials has a second top electrodeand a second bottom electrode, wherein the second linear dielectricmaterial or the second paraelectric material is between the second topelectrode of the second planar stack of materials and the second bottomelectrode and the second planar stack of materials, wherein the secondbottom electrode is on the second pedestal, wherein the second inputline is on the second top electrode of the second planar stack ofmaterials.
 9. The apparatus of claim 7, wherein the first lineardielectric material includes one of: SiO2, Al2O3, Li2O, HfSiO4, Sc2O3,SrO, HfO2, ZrO2, Y2O3, Ta2O5, BaO, WO3, MoO3, or TiO2.
 10. The apparatusof claim 3, wherein the device is a pull-up device coupled to thesumming node and a power supply rail.
 11. The apparatus of claim 10,wherein the circuitry is to set logic levels of the first input, thesecond input, and the third input to logic high, and the control toenable or turn on the pull-up device in the first operation mode toadjust a threshold of the gate to
 2. 12. The apparatus of claim 10,wherein the pull-up device is controlled by the control, whereinvoltages on the first input, the second input, and the control are setin the first operation mode to adjust a threshold of the apparatus,wherein the control is to cause the pull-up device to be off in thesecond operation mode, wherein the second operation mode occurs afterthe first operation mode.
 13. The apparatus of claim 1, wherein thefirst capacitor, the second capacitor, or the third capacitor include: alinear dielectric material includes one or more of: Si, Al, Li, Hf, Sc,Sr, Zr, Y, Ta, Ba, W, Mo, or Ti; and a top electrode and a bottomelectrode, wherein the linear dielectric material is between the topelectrode and the bottom electrode, wherein the top electrode or thebottom electrode include one or more of: Cu, Al, Ag, Au, W, or Co. 14.The apparatus of claim 1, wherein the first capacitor, the secondcapacitor, or the third capacitor include paraelectric material whichincludes one of: SrTiO3, Ba(x)Sr(y)TiO3 (where x is −0.5, and y is0.95), HfZrO2, Hf—Si—O, BaTiO3, La-substituted PbTiO3, lead zirconatetitanate, or PMN-PT (lead magnesium niobate- ead titanate) based relaxorferroelectrics.
 15. An apparatus comprising: a first input; a secondinput; a third input; a fourth input; a fifth input; and a gate toprovide an output which is a consensus of the first input, the secondinput, and the third input, wherein the output is coupled to the fourthinput and the fifth input, wherein the gate has a plurality ofcapacitors that are planar capacitors, and wherein the planar capacitorsare vertically stacked.
 16. The apparatus of claim 15, wherein theoutput is a logic high when the first input, the second input, and thethird input are logic high, wherein the output is a logic low when thefirst input, the second input, and the third input are logic low,wherein the output retains its logic state when at least one of thefirst input, the second input, or the third input is a logic 1 and whenthe at least one of the first input, the second input, or the thirdinput is a logic
 0. 17. The apparatus of claim 15, wherein the gatecomprises: a first capacitor having a first terminal coupled to thefirst input, and a second terminal coupled to a summing node; a secondcapacitor having a third terminal coupled to the second input, and afourth terminal coupled to the summing node; a third capacitor having afifth terminal coupled to the third input, and a sixth terminal coupledto the summing node; a fourth capacitor having a seventh terminalcoupled to the fourth input and the fifth input, and an eighth terminalcoupled to the summing node; a fifth capacitor having a ninth terminalcoupled to the fourth input and the fifth input, and a tenth terminalcoupled to the summing node, wherein the first capacitor, the secondcapacitor, the third capacitor, the fourth capacitor, and the fifthcapacitor are part of the plurality of capacitors; and a device coupledto the summing node and a supply rail, wherein the device iscontrollable by a control.
 18. The apparatus of claim 15 comprises acircuitry to adjust a function of the gate by controlling the adjustablethreshold in a first operation mode, and wherein the circuitry is toallow the gate to operate in accordance with the function in a secondoperation mode.
 19. A system comprising: a memory to store one or moreinstructions; a processor circuitry to execute the one or moreinstructions; and a communication device to allow the processorcircuitry to communicate with another device, wherein the processorcircuitry includes a consensus circuity which comprises: a first input;a second input; and a consensus circuitry coupled to the first input andthe second input, wherein the consensus circuitry is to generate aconsensus output which is indicative of a consensus of the first inputand the second input, wherein the consensus circuitry comprises a gateto receive the first input, the second input, and a third input, whereinand the third input is coupled to an output of the gate which is theconsensus output, wherein the gate comprises: a first capacitor having afirst terminal coupled to the first input, and a second terminal coupledto a summing node; a second capacitor having a third terminal coupled tothe second input, and a fourth terminal coupled to the summing node; anda third capacitor having a fifth terminal coupled to the third input,and a sixth terminal coupled to the summing node, wherein the firstcapacitor, the second capacitor, and the third capacitor are planarstacked capacitors.
 20. The system of claim 19, wherein the gatecomprises: a first metal layer extending along an x-plane; a secondmetal layer extending along the x-plane, wherein the second metal layeris above the first metal layer; a first via extending along a y-plane,wherein the y-plane is orthogonal to the x-plane, wherein the first viacouples the first metal layer with the second metal layer; a second viaextending along the y-plane, wherein the second via couples the secondmetal layer, wherein the second via is above the first via; a firstpedestal on the first metal layer, wherein the first pedestal islaterally offset from the first via; a second pedestal on the secondmetal layer, wherein the second pedestal is laterally offset from thesecond via, wherein the summing node is coupled to the first via; afirst input line extending along a z-plane, wherein the z-plane isorthogonal to the x-plane and the y-plane, wherein the first input iscoupled to the first input line; and a second input line extending alongthe z-plane, wherein the second input is coupled to the second inputline; wherein the first capacitor comprises a first planar stack ofmaterials including a first linear dielectric material or a firstparaelectric material, wherein the first planar stack of materials has afirst top electrode and a first bottom electrode, wherein the firstlinear dielectric material or the first paraelectric material is betweenthe first top electrode and the first bottom electrode, wherein thefirst bottom electrode is on the first pedestal, wherein the first inputline is on the first top electrode; and wherein the second capacitorcomprises a second planar stack of materials including a second lineardielectric material or a second paraelectric material, wherein thesecond planar stack of materials has a second top electrode and a secondbottom electrode, wherein the second linear dielectric material or thesecond paraelectric material is between the second top electrode of thesecond planar stack of materials and the second bottom electrode and thesecond planar stack of materials, wherein the second bottom electrode ison the second pedestal, wherein the second input line is on the secondtop electrode of the second planar stack of materials.